#transcript #pcb #layout #predictable-designs #youtube # 11 PCB Layout Rules to NEVER Break — Predictable Designs YouTube's manually-uploaded English captions (yt-dlp, `en` subs — not auto-generated, so names and punctuation are clean), collapsed into ~30 s paragraphs. Distilled in [[PCB Layout Rules to Never Break]]. Source: https://www.youtube.com/watch?v=juOTCCq_eig · Predictable Designs (John Teel) · uploaded 2026-09-03 · 12:00 # Links from the description - PCB Layout Rules Checklist: https://predictabledesigns.com/pcb-layout-rules-checklist/ # Transcript **[0:00](https://youtu.be/juOTCCq_eig?t=0)** Two boards can be built from the exact same schematic, and one works perfectly while the other fails EMI testing or resets randomly or has almost no wireless range. The layout is where the real physics happens, and small placement and routing decisions can make or break your entire product. So, in this video, I'm counting down 11 PCB layout rules that you should never break, ending with the one that's the most invisible and the most expensive to fix. And for every single one, I'll tell you what to do instead. Hi, I'm John **[0:34](https://youtu.be/juOTCCq_eig?t=34)** Teal. I spent over a decade as a microchip design engineer at Texas Instruments. Then, I developed and launched my own product, and now I help others do the same inside my hardware academy. Okay, let's get started. Rule number 11, never use via pad without knowing the cost. So via impad means placing a via directly inside a components solder pad instead of next to it. I know it's tempting because it saves space and for dense parts like fine pitch BGAS, it's sometimes really the only option. But there are two costs **[1:07](https://youtu.be/juOTCCq_eig?t=67)** that most people don't see coming. First, during assembly, the molten solder wicks down into the open via like a straw, which starves the joint and leaves you with a weak or even open solder connection. Second, the fix for that is having your board fab fill each via with epoxy and plate copper over the top. And that process adds real money to every single board that you ever build. So unless you truly need it, place VAS next to the pad and connect them with a short trace. And if your design does **[1:40](https://youtu.be/juOTCCq_eig?t=100)** require a via impad, specify field and capped VAS in your fab notes and budget for that extra cost from day one. Real quick before we go any further, I put together a free PCB layout checklist that covers every rule in this video so you can run through it before ordering your own boards. Links in the description below or you can scan this QR code. Rule number 10, never design a board without test points. A board with no test points can't be tested in production. That means you're either shipping units that were never verified **[2:13](https://youtu.be/juOTCCq_eig?t=133)** or you're paying someone to probe every single board by hand. Factories test boards in production using a fixture with spring-loaded pogo pins. And those pins need dedicated copper pads to land on. If you didn't put those pads in your layout, there's nowhere for the pins to go. and adding them later means a new board revision. The good news though is that test points are basically free since you're just placing small exposed copper circles on your signals and power rails. Add them to every power rail, every communication bus, and anything **[2:46](https://youtu.be/juOTCCq_eig?t=166)** that you'd need for programming or debugging the board. Test points are also a lifesaver during debugging, especially with leadless packages like QFNs and BGAS where the pins are hidden underneath the chip and there's nothing for you to probe. Rule number nine, never skip a thermal path for hot components. A voltage regulator that works fine for 10 minutes and then browns out is commonly a layout problem and not necessarily a problem with the component. Many regulators and other hot components dissipate their heat through **[3:19](https://youtu.be/juOTCCq_eig?t=199)** an exposed pad on the bottom of the package called a power pad. That pad needs somewhere for the heat to go. And on most boards, that means an array of thermal VAS connecting it down to a large copper port on another layer. And yes, those thermal VAS are technically via in pad, but a power pad is the one place where it's normally acceptable since a little solder wicking there mostly causes small voids instead of failed connections. Skip those VAS and the heat just piles up until the part hits thermal shutdown and then your **[3:51](https://youtu.be/juOTCCq_eig?t=231)** product resets over and over out in the field. So follow the landing pattern in the data sheet exactly, including the recommended via array. And give the part as much copper area as you can spare. Copper is free and it's the cheapest heat sink you'll ever get. Rule number eight, never run high-speed traces near the board edge. High-speed traces routed near the edge of the board are a classic way to fail EMI testing. Near the edge, the electric fields around a trace are no longer fully contained between the trace and its ground plane. Part of the **[4:25](https://youtu.be/juOTCCq_eig?t=265)** field fringes out past the edge of the board, and that fringing field radiates like a little antenna. Everything will look fine on your bench, but the antennas at the test lab will pick it up immediately, and every failed EMI scan cost you money and weeks of schedule. The fix is to keep fast signals like clocks, USB, and memory buses away from the board edge by at least four to five times the distance between the trace and the ground plane below it, which on most boards works out to around a millimeter **[4:58](https://youtu.be/juOTCCq_eig?t=298)** or more. Also, be sure to route on inner layers whenever possible. Rule number seven, never leave the board without stitching VAS. Stitching VAS are the rows of ground VAS that tie your ground planes together across the board. Without them, ground currents on different layers can't take the shortest path back to their source, and the gaps between your planes start acting like slots that leak radiation. Stitching VAS along the board edges also form a fence that helps contain noise inside your board. I recently reviewed a board that **[5:31](https://youtu.be/juOTCCq_eig?t=331)** looked clean everywhere else, but it had no stitching VAS, and we caught it right before the FAB order went out. Adding them cost nothing, and it meaningfully improves the product's odds of passing FCC testing on the first try. So, sprinkle ground stitching VAS everywhere possible across the board, especially along the edges, around any high-speed routing, and around any RF circuits or antenna feed lines. Rule number six, never ignore the switching regulator hot loop. Every switching regulator has a **[6:05](https://youtu.be/juOTCCq_eig?t=365)** hot loop, which is the current path where current starts and stops in just a few nanconds. That fast changing current makes the loop behave like a tiny transmitting antenna. And the bigger the loop area, the more noise it sprays across your board. Chip makers like TI and analog devices publish recommended layouts in their switching regulator data sheets. And those layouts exist specifically to keep this loop tiny. Place the input capacitor as close to the regulator as physically possible. Keep the loop on a single layer and copy **[6:39](https://youtu.be/juOTCCq_eig?t=399)** the data sheet layout instead of improvising your own. Rule number five, never route differential pairs like ordinary traces. Differential pairs like USB, Ethernet, and HDMI carry equal and opposite signals on two traces, and the receiver only reads the difference between them. This makes them extremely immune to noise because interference hits both traces equally and cancels out at the receiver, but only when the layout is done correctly. For that to work, both traces need to have their **[7:11](https://youtu.be/juOTCCq_eig?t=431)** length matched. They need to have a controlled impedance, an unbroken reference plane underneath, and no stubs hanging off of either line. Get any of those wrong and the signals arrive skewed or reflected, which turns into random errors that are brutal to debug. Your PCB software has built-in tools for properly routing differential pairs, so be sure to use them. Rule number four, never starve a power trace or via. A power trace that's too thin drops voltage under load, heats up, and in the worst case burns right off the board. **[7:45](https://youtu.be/juOTCCq_eig?t=465)** The same goes for VAS, since a single small via might only handle an amp or so before it becomes the bottleneck. Product creators often route power using the same default trace width as their signals, and everything seems fine at low current during early testing. Then the product hits a high load condition. The supply rail sags and the microcontroller resets at the worst possible moment. Trace width calculators are free and take seconds to use. So size every power trace for its actual current under worst case conditions with plenty of margin. For higher currents, **[8:20](https://youtu.be/juOTCCq_eig?t=500)** use copper pores instead of traces and always place multiple VAS in parallel wherever power changes layers. Rule number three, never put copper under an antenna. Copper placed under an antenna will kill your wireless range. An antenna works by coupling energy into the space around it. And a ground plane or any copper sitting underneath it or near it d-tunes the antenna and absorbs the energy before it ever leaves your board. Every antenna and every pre-certified wireless module has a keep **[8:53](https://youtu.be/juOTCCq_eig?t=533)** out zone defined in its data sheet, which is just an area where you're not allowed to put copper traces or components on any layer. The same goes for metal mounting screws and standoffs. So, keep those away from the antenna, too, since metal that close will d-tune it just like copper does. This one also has a certification angle to it because a pre-certified module is only certified when it's used the way the data sheet specifies. Violate this keepout area and the module in your product no longer performs as certified, which can come **[9:26](https://youtu.be/juOTCCq_eig?t=566)** back to bite you during compliance testing. Look at any dev board for a wireless module and you'll find a bare region around the antenna and you should do the same thing on your layout. Rule number two, never place decoupling capacitors far from the pin. Decoupling capacitors only work when they're close to the power pin that they're protecting. A decoupling cap acts like a tiny local energy tank that supplies the chip during sudden current spikes faster than the main power supply could ever respond. Every millimeter of trace **[9:59](https://youtu.be/juOTCCq_eig?t=599)** between the capacitor and the pin it's protecting just adds inductance. and inductance resists exactly those fast current changes. Put the cap too far away and you've built a filter that blocks the capacitor from doing its one job. So, the chip supply dips and you get random glitches and resets. So, place the capacitor close to the pin, connect it with a short wide trace, and drop ground VAS right at the capacitor's pad. To make all this easier for you, don't forget to grab that free layout checklist that I mentioned earlier in **[10:32](https://youtu.be/juOTCCq_eig?t=632)** the links in the description. Rule number one, never route signals across a plane split. Routing a signal across a split in your ground plane or power plane is the most invisible and most expensive mistake on this entire list. Every signal current has to return to its source. And at high frequencies, that return current flows in the plane directly underneath the trace. When the trace crosses a plane split, the return current can't follow it. So, it detours all the way around the gap. That detour creates a huge loop that radiates noise, **[11:06](https://youtu.be/juOTCCq_eig?t=666)** couples interference into every nearby circuit, and is a leading cause of both EMI failures and mystery glitches that nobody can reproduce. And nothing about it looks wrong since the trace appears perfectly normal, and every net checks out in your design software. Now, to be clear, plane splits themselves are sometimes the right choice, like separating a sensitive analog section. And the rule is about what you route over them. So, before you order boards, check every trace against the planes beneath it on every layer and reroute anything that crosses a gap. And if **[11:41](https://youtu.be/juOTCCq_eig?t=701)** you'd like experienced engineers to review your layout and catch these exact mistakes before you spend money on boards, that's what my hardware academy is for. And if you found this video helpful, then this video right here on the seven protections that you should never ship a product without is the one I'd suggest you watch next.