#transcript #pcb #copper-pour #phils-lab #youtube # PCB Copper Pours 101 — Phil's Lab #176 Auto-generated YouTube captions (yt-dlp, `en-orig` auto-subs), collapsed into ~30 s paragraphs. Caption errors are left as-is ("paw" / "pore" / "PS" = pour(s), "VA" / "VAS" = via(s), "GLC" = JLC, "Alum" / "Alton" = Altium, "relieves" = reliefs). Distilled in [[PCB Copper Pours 101]]. Source: https://www.youtube.com/watch?v=Ao2HUjjhlmQ · Phil's Lab · uploaded 2026-07-31 · 26:47 # Links from the description - PCB Stack-Up and Build-Up: https://www.youtube.com/watch?v=QAOEtfvCaMw - PCB Design Rules 101: https://www.youtube.com/watch?v=zeH3WbMWvdg - Secrets of PCB Optimisation: https://www.youtube.com/watch?v=0RyBCnowLsI - Rick Hartley & Robert Feranec video: https://www.youtube.com/watch?v=52fxuRGifLU - Thermal Relief Design Guide: https://resources.altium.com/p/thermal-relief-design # Chapters - [0:00](https://youtu.be/Ao2HUjjhlmQ?t=0) Intro - [2:57](https://youtu.be/Ao2HUjjhlmQ?t=177) Altium Develop (Ad) - [4:02](https://youtu.be/Ao2HUjjhlmQ?t=242) Design Rules - [10:52](https://youtu.be/Ao2HUjjhlmQ?t=652) Pour Order (Priority) - [11:49](https://youtu.be/Ao2HUjjhlmQ?t=709) Thermal Relief - [22:50](https://youtu.be/Ao2HUjjhlmQ?t=1370) Copper Balance - [25:20](https://youtu.be/Ao2HUjjhlmQ?t=1520) Hatching - [26:25](https://youtu.be/Ao2HUjjhlmQ?t=1585) Outro # Transcript **[0:00](https://youtu.be/Ao2HUjjhlmQ?t=0)** In this video, I'd like to cover the basics of copper PS, polygon poles, fills, planelets as they relate to printed circuit board or PCB design. We'll cover the critical aspects of polygon poles and copper fills, when to use them, when not to use them, what they are for, and what to pay attention to, and how to try and avoid them causing issues and actually being a benefit to your design. The PCB you're seeing here utilizes quite a number of polygon pores and cover pores. Essentially, a copper pole is just a polygon fill that floods a part of the board area with copper and is assigned to a particular net. This is very very **[0:33](https://youtu.be/Ao2HUjjhlmQ?t=33)** similar to these traces you're seeing here, but they serve different purposes and are typically quite a bit larger in terms of area and and then of course also volume. You might have polygon pores that span the entire board such as this top ground polygon paw. You might have smaller polygon pores that only span a small subsection and are used for instance for as larger current carrying traces or polygons. And you might see polygon pores or copper fields used as reference planes. For instance, for internal layers. In this particular four layer board, we have layer 2 and layer **[1:05](https://youtu.be/Ao2HUjjhlmQ?t=65)** three. Those are essentially board spanning copper paws or polygon fills. Again, they are all respectively tied to their own net. A lot of the times this will be connected to ground or reference or 0 volt. So that for instance in this case on layer 1 when we have traces running on layer one the layer adjacent is a nice solid reference plane a reference copper pore which provides a low impedance return path when used as a reference plane. This is of course useful for the return path itself for EMI and signal integrity purposes. But polygon pores in general can provide far **[1:39](https://youtu.be/Ao2HUjjhlmQ?t=99)** more uses than that. They can act as heat sinks. They can allow for thermal spreading. Can use them to balance the copper distribution across various layers and for our power distribution within our printed circuit board. For more information on stackup buildup and reference planes when you would use polygon PS for that and essentially in every PCB design you would do that. I can suggest checking out video number 56 on my channel titled PCB stackup and buildup. And I also have a summarized article on resources.outium.com. Again links will be in the description box below. These polygon PS, these copper fills should never be used simply **[2:13](https://youtu.be/Ao2HUjjhlmQ?t=133)** for decorative reasons. Every single one of these fills and PS has a particular reason for being there. They should never just been thrown on a board arbitrarily. There's always a use to them. And I'd like to show you again some of the basic dos and don'ts as a little starter guide to using polygon paws and what to watch out for. Again, this is a 101 or basics type video. If you'd like to go into a bit more depth, there are some great videos by Robert Ferin and Rick Hartley. for instance, to how to decide on a PCB layer ordering, pouring and stackup. Links will be in the description box below. And this video on the Alteium Academy YouTube **[2:45](https://youtu.be/Ao2HUjjhlmQ?t=165)** channel called Secrets of PCB Optimization again with Rick Hartley, which goes more into the design for manufacturing aspects, which we will be covering in a tiny bit in this video as well. Again, links in the description box below. A huge thank you to Alum for sponsoring this video. I use Alim develop which includes Alum Design and Alim 365 in my everyday day-to-day work life as well as for creating content for this channel and also use out designer as part of Alton Develop to design and manufacture this digital audio processing board that we'll be seeing and using in this particular video. Out in develop enables multiddisciplinary **[3:19](https://youtu.be/Ao2HUjjhlmQ?t=199)** teams to design, develop and manufacture high quality hardware products with ease and efficiency all the way from co-creation of designs be that parts library management, schematic design, hardware design, requirements management, all the way through managing your supply chain, manufacturing, and of course generating and maintaining all of the relevant data as part of an entire project. You can take a tour of Alton Develop and I'll leave links to this in the description box below which guides you through all of the parts that Alton Develop helps you manage in your project and product design process if you're **[3:52](https://youtu.be/Ao2HUjjhlmQ?t=232)** interested. Again, I'll leave links in the description box below, but you can get started with Alton Develop and you can try this out for yourself risk-f free for 30 days. Links will be in the description box below. The first item I'd like to discuss when talking about copper paws is that of the pore settings as well as the design rules that relate to these polygon pores and copper fills. As with traces, pads, components, and any other feature that's on our printed circuit board, with polygon pores as well, and copper fills, regardless of which layer they are on, we need to adhere to certain design rules to make sure our printed circuit board is **[4:25](https://youtu.be/Ao2HUjjhlmQ?t=265)** manufacturable, that we have minimal issues with assembly, hopefully none, of course, and of course that our Polygon PS aid our overall EMI performance and signature as well as signal integrity. A large part of that especially when with regards to manufacturability is that of clearance. So for instance I have this tiny 3.3 volt polygon pore here. This has certain clearance boundaries and is governed by certain clearance rules and constraints set in our design rules. So that could be the actual polygon to polygon clearance something around.35 mm here. This could be the clearance **[4:59](https://youtu.be/Ao2HUjjhlmQ?t=299)** between the polygon pore and SMD pads to traces to traces within the ONET to features within the ONET and so on. You can find these rules under design rules in out designer and any ECAD tool will have these sets of rules. If I go to the clearance section, we can see we have a particular row for copper. So we have copper to track, copper to SMD pad, copper to thor pad, via and copper to copper as well as this single entry of copper to hull. Now, these all have to be set responsibly depending on your design constraints, depending on your manufacturer and manufacturability. I **[5:32](https://youtu.be/Ao2HUjjhlmQ?t=332)** have a whole video on PCB design rules 101. That's video number 170 on my channel. And again, I'll leave links to this in the description box below. And this goes more into detail of how to set up your design rules and how to assign them either locally or globally to the entire board. In essence, we want to make our PCB manufacturable not just for one manufacturer, but for a large subset of large group of manufacturers in general or without going near manufacturing minimum constraints and minimum levels. We want to make it reliably manufacturable with a high yield. That is when they are manufactured. A lot of the printed circuit boards survive without defects. **[6:05](https://youtu.be/Ao2HUjjhlmQ?t=365)** If you go to your preferred manufacturer of choice, in this case I'm going to GLC PCB, they will always have a capabilities or manufacturing capabilities section. And from this you can then extract the design rules you need to use for your printed circuit board and also for your copper paws. Now they might be under the traces section because essentially traces are very very similar to copper paws. They have essentially the same clearance constraints between traces and copper fills and copper paws. So from this we can take minimum trace width minimum spacings which apply to both traces and copper features and and copper paws as **[6:38](https://youtu.be/Ao2HUjjhlmQ?t=398)** well. And here GLC says they can go down to 0.1 millimeters for one and two layer boards and 0.09 mm for multi-layer boards above two. Now of course these are absolute minimum capabilities and I'd strongly suggest staying away from these if your design allows. And if you need to go to these minimum capabilities only do that locally wherever you need them on your printed circuit board design. Again refer to the design rules 101 video how to set up local and global design rules. We always want to add on some sort of margin and set our design rules fairly straight. So not going down to these minimums. So this is for trace **[7:11](https://youtu.be/Ao2HUjjhlmQ?t=431)** widths and spacing. Then there's going to be design rules such as the same net track to track spacing or copper feature to copper feature spacing in a layer via hole to copper clearance and so on. And these are again the absolute minimums that this particular PCB manufacturer can manufacture. In your e-car tool, you would then transfer these numbers over and add some sort of margin on top depending on what your design allows. Again, stay away from minimums. So, we have these clearance settings here. We also have minimum widths, which is also important for our copper features because, for instance, looking at this 1.2 volt copper paw, which essentially **[7:46](https://youtu.be/Ao2HUjjhlmQ?t=466)** just distributes this 1.2 volt power net across parts of the board that has to neck down in certain areas. For instance, this area here, we can see we have a a narrower neck of about45 mm. If we were more constrained and we had to make this neck even smaller, we only want to do this necking down when we really really need to. We don't want to keep this current carrying or power carrying polygon paw narrower than we need to. And we always expand when we have the space. But in any case, even when we have to neck down, we have to stay above a certain minimum. So a similar rule that applies to traces, we **[8:19](https://youtu.be/Ao2HUjjhlmQ?t=499)** have to go above a certain minimum trace width. Of course, also applies to copper paws as well. And having clicked on this polygon paw in the right hand side we can see various properties and one of these properties is this remove next less than feature. We also have this check box which says obey rules and that's obeys the rules we set out in our design rules. I can also uncheck that and say okay it needs to be larger than6 mm. If I report that we can see immediately that this connection now breaks because alum or your ecad tool cannot connect this sliver here without violating the rule we set in place. So **[8:52](https://youtu.be/Ao2HUjjhlmQ?t=532)** keep in mind also we need not just clearance rules but also minimum polygon pore width rules as well. And again only neck down when you really need to. These clearance and minimum copper paw width rules are in place of course to make this board manufacturable. If the features are too close to each other you might risk the chance of shorts from manufacturing tolerances. If you leave next too narrow they might not connect properly. You might have risk of breakages and so on. And in particular with higher voltage designs, you need to take into account your creepage and clearance requirements. So you might need larger clearances between various **[9:26](https://youtu.be/Ao2HUjjhlmQ?t=566)** nets, especially if they're high voltage nets and so on. Another feature other than of course the clearances and the minimum widths are minimum island areas. On the right hand side, you might have already spotted this. We have this remove islands less than 5 square meters in this particular case. And we can change how small these islands can be. And this is particularly useful if you're doing polygon cleanup. And for example, you might want to remove small islands such as this if they're not stitched properly or if you cannot stitch them properly. We'll come to stitching beers later on as well. So there's various other parameters that we can use here. Your design rules you can **[10:01](https://youtu.be/Ao2HUjjhlmQ?t=601)** set up depending on the layer they are on. So layer 2, layer three, because they're internal layers will likely have different constraints and different requirements to those that are poured on for instance outer layers. And this could be because pouring, for instance, if you're using controlled impedance traces such as the USB 2.0 and USB 3 super speed differential pairs we have here, we want to keep a larger clearance away from these differential pairs to our polygon or copper paws because if we bring these planelets closer to these traces, that'll actually throw off the **[10:33](https://youtu.be/Ao2HUjjhlmQ?t=633)** impedance of these traces. And for controlled impedance, you of course want to have them be the impedance you calculated them to be at. So, if I go to design rules, I've also set clearances for layer 1 and layer 4 that are slightly different to my inner layer clearance rules. Again, one reason being that I don't want them to be too close to my controlled impedance traces. Also, because we have multiple different polygon pores and little planets on the top and bottom layers. What is also important is the polygon paw order or priority. Which polygon pores do you want to pour first? In the case of layer **[11:06](https://youtu.be/Ao2HUjjhlmQ?t=666)** one, I want to pour all these smaller polygons first and only apply my ground polygon paw that covers essentially the entire surface area of the top and bottom layers. I want to apply that last and that we can deal with priorities. If I go to tools, polygon paws, polygon manager, we can see I have a certain pore order. So I start with my smaller nets and only at the end I pour my ground polygon p. If I were to do my ground polygon port a different order and then repour all, you can see because the ground polygon pore takes priority, this Vbus Fnet or polygon pore is not **[11:41](https://youtu.be/Ao2HUjjhlmQ?t=701)** poured correctly. That's why polygon pore priorities are very important and something you need to consider in your design as well. So this is it with it properly restored. Another large part when using polygon and copper PS is the discussion on thermal release versus direct connections. Direct connections are when you pour a polygon paw and as the name implies the polygon itself flows all over any features that are within that polygon paws area. So for instance here I have this pad and because this is a direct connection you **[12:14](https://youtu.be/Ao2HUjjhlmQ?t=734)** can see the polygon pore easily flows all over that area encompassing the pad encompassing this other pad encompassing these v and so on. This is in contrast to thermal reliefs. For instance, a thermal relief. We can see for the ground polygon pore connected to these ground pads of for instance this 0603 capacitor here. We have not the copper flowing all over the pad, but rather we have these little spokes that attach at suitable points from the polygon pore to this pad. And there's various reasons for doing one or the other. Direct **[12:47](https://youtu.be/Ao2HUjjhlmQ?t=767)** connect would typically be preferred if it were to come with certain manufacturability issues. Direct connect is great because we have essentially a whole an entire connection to the relevant pad. We have better thermal conductivity between the various features that connect this polygon pore. But we have the issues that if we have copper imbalance, for example, if we have this large polygon pore, this large thermal mass of ground and then we connect that directly to a very small component just on one side and the other side of that component has just a **[13:19](https://youtu.be/Ao2HUjjhlmQ?t=799)** relatively small thermal mass in terms of the copper area attached to it. That can lead to some severe manufacturability issues because again the ground here would act as a massive heat sink whereas the other side wouldn't have the same thermal mass. For example, if this small component would instead be just a solid connection, we have this large thermal imbalance, which means this ground pad number two doesn't heat up as quickly as our ground pad one. Now, this of course depends on the soldering methodology. If it's with an iron or reflow oven temperature profile and so on, but this can be a rather **[13:52](https://youtu.be/Ao2HUjjhlmQ?t=832)** large issue in particular for smaller SMD components, that can lead to what's known as tombstone. So on one side because of the different connectivities and heat profiles either side of the component, the component might actually move up and sit up like a little tombstone, a little gravestone. That's of course a rather large manufacturing defect and something we would want to avoid. So therefore, instead of doing direct connections depending on the size of and difference between copper balances either side of the component, we might add these or typically add these thermal relieves. Now these thermal relieves other than just having **[14:25](https://youtu.be/Ao2HUjjhlmQ?t=865)** a different essentially thermal connection will of course also change the inductive properties or the connection properties at these spokes. So a connection that has thermal relieves will typically have a higher inductance compared to earth solid connection. That can of course matter for decoupling and power delivery as well. The same principle applies also to through all connections. For example, here we have this through pad because either this will be wave soldered or manually soldered with a soldering iron. And if you have a a solid connection to all of these ground poles and planes, we have these essentially on four layers. **[14:57](https://youtu.be/Ao2HUjjhlmQ?t=897)** If we had a solid connection here, that would be very very difficult to solder, especially if it's for hand soldering. But of course, it can also be helpful for wave soldering as well. So, we need to take this into account with copper paws for SMD components and also for through hole components. Now, there's always going to be a trade-off again for thermals, for inductance, and solderability, manufacturability. That's something you have to keep in mind too. What is the component connected to? What is the pin connected to? And for instance, for these SMD components, what are the other pins connected to? Is there thermal imbalance? Is there copper imbalance? And so on. As a very very general guideline, I would suggest using **[15:31](https://youtu.be/Ao2HUjjhlmQ?t=931)** thermal relieves, especially if you're doing these large ground polygon pores and floods on your top and bottom layers, especially if you have these rather large imbalances between one side of the component and the other. Now, of course, this can also be the case for multi-pin components, more than two pins. Again, check your copper balances. Check the way this board is being assembled and manufactured. But again, polygon poles, copper fills can act great as heat sinks, and that's often times what's wanted. So, for instance, for this QFN exposed pad in the center, that's connected to all of the ground copper that exists on the board, at **[16:05](https://youtu.be/Ao2HUjjhlmQ?t=965)** least locally around it. That is very useful as a heat sink. But again, there are manufacturing challenges with assembly that come with this. There's always a balance in terms of how these spokes are sized. These thermal relief spokes are sized. You can go with an IPC guideline for this. This of course depends on the pad size, what kind of current and power demands you have flowing into and out of that component, what inductance requirements you have, and so on. But as a general rule of thumb, you would take if it's a if it's a square pad, you would take a pad side. So if that's 1 millm, take 60% of that **[16:40](https://youtu.be/Ao2HUjjhlmQ?t=1000)** and then divide by the number of spokes you have connecting to this. So a 1 millm pad, a 1 millm square pad would give 0.6 mm. If you have two spokes, that would be 0.3 mm. If you have four, that would be 0.15 mm spoke width. Again, this depends on current. It depends on the pad shape, pad size. But that's a general rule of thumb. You can check out the IPC 2221 and 2222 standards for more details on this. Thermal relieves exist for both SMD pads, throughhole pads, but of course for VAS themselves. And you've probably **[17:13](https://youtu.be/Ao2HUjjhlmQ?t=1033)** seen here my VA do not have any thermal relieves on them. And this is what I would suggest as an as a complete default. I don't think I've ever used thermal relieves on VAS. The way you can set that up depends on your ECAD tool as well. If we go to design rules, then go to polygon connect. There is the simple constraints option where everything just has a certain style. So it's relief connect, direct connect. But I go with advanced and I can change my thermal relief properties depending on the connection type. So that's through hole pad, if it's SMD pad, or if it's a V connection. Here you can set the air gap **[17:46](https://youtu.be/Ao2HUjjhlmQ?t=1066)** width as well as the conductor width and how many conductors you have. Again, either follow this 60% rule divided by the number of conductors or generically I typically leave that if I don't have any particular requirements for 0603ish components at about 3.3 or 0.25.25 25 for SMD pads and similarly for throughhole pads. That is a pretty good starting point I found. Also for hand soldering but via connections again I would personally always leave as direct connect unless there's a very very good reason to do otherwise. Now of course other than global rules you can set them **[18:19](https://youtu.be/Ao2HUjjhlmQ?t=1099)** per pad. So if I click on a certain pad here go to the properties on the right hand side you can see I can click on relief and I can change the relief to whatever I want for that particular pad. So you can set them individually for pads. And of course, you can create your own custom design rules that pick out certain pads if they are have these certain dimensions, then apply a certain relief like so or like so. So you don't have to use just just this one certain overall design rule. What you've probably also really noticed is the amount of these grounded vas that are scattered seemingly around the board. **[18:51](https://youtu.be/Ao2HUjjhlmQ?t=1131)** Those are what's known as stitching vas. And these are very very important particular if you have multiple same net polygon pores around the board. These VAS are placed at certain intervals and certain spacings all across the board anytime we have a polygon paw and they tie all of these ground fills and ground paws together again at somewhat regular intervals along the Z axis. So, so vertically, if we do this side on view, we can see all these stitching views all around the board that tie all of these **[19:25](https://youtu.be/Ao2HUjjhlmQ?t=1165)** planes and copper fills of one particular net together. There are plenty of reasons for this. One of the reasons is that for every single ground pad of top and bottom layer components, we want to tie this pad with a low impedance, low inductance connection to the internal reference to the internal ground planes again to lower the impedance of that connection. So part of these grounded VAS are just simply the the via connection to the internal planes for all of these top and bottom layer ground connections. But the remaining connections which aren't next **[19:58](https://youtu.be/Ao2HUjjhlmQ?t=1198)** to these ground pads are again also these stitching behind into the RF and high frequency bands that tie all of these polygon PS together to maintain a low impedance across a large bandwidth. In the previous video on the channel on via fencing and edge plating, I go into a bit more detail on via stitching, but we have them around the perimeter. But again tying all the copper polygon paws together to maintain this lo pins connection throughout all of these ground polygon paws and planes and **[20:31](https://youtu.be/Ao2HUjjhlmQ?t=1231)** layers. If we didn't have these stitching VAS for instance if I had this region like so where I basically just have the ground v next to the ground pads we have this unconnected polygon pore here. And this pore if not stitched properly and stitched correctly can actually resonate and essentially form an antenna because it's only fed very simply speaking by the left hand side and the right hand side here is essentially floating at RF without these stitching VAS. So we place these stitching VAS down also for EMI and signal integrity reasons that we don't **[21:04](https://youtu.be/Ao2HUjjhlmQ?t=1264)** get these unwanted resonators. The larger the pore, the larger these resonant planes and resonant areas without stitching, the lower the resonant frequency will be typically for these patches and these essentially form little patch antennas. The simple rule of thumb for spacing is analyzing the maximum frequency of interest in your design. So if that's analog, that's very straightforward. V equals lambda F. But for digital, we want to correlate the rise and fall times of our digital signals to an approximate knee frequency. So our somewhat of an analog bandwidth. We figure out the maximum **[21:36](https://youtu.be/Ao2HUjjhlmQ?t=1296)** frequency. We calculate the wavelength. Of course, taking into account the speed of light and the reduction of the speed because of the dilectric material. And then we take that wavelength and divide that by some sort of constant. So that could be eight. But if we want to be very stringent in that we divide by 20. So the wavelength divided by 20 might be a very very strict stitching via approach. And we do that all across the plane all across the board wherever we have these polygon PS. This is something I typically do at the end of the board. But I try to plan in stitching views while I do the design. You don't want to be left with loads of **[22:10](https://youtu.be/Ao2HUjjhlmQ?t=1330)** areas of polygon poles that aren't stitched properly. Now, areas that you can't stitch properly, what you can do, for example, if we have this region here, which isn't providing terribly much use, what we can do is add in a polygon paw cutout. So, I can press P and then go to polygon paw cutout and just very simply drawing. I can draw this cutout area very badly drawn, but something like this. And you can see that gets rid of this polygon pore here in case we want to do some polygon paw cleanup. In case you don't want to stitch, we could add in these little regions. And these could be multi-layer. These can be per layer depending on **[22:44](https://youtu.be/Ao2HUjjhlmQ?t=1364)** where you place these regions. And that's what I typically do at the end is also this polygon pore cleanup using these polygon pore cutouts. Now the question is, is there actually any benefit to pouring top and bottom layer copper? Often times you can actually make things worse by pouring your signal and power layers with copper, especially if it's uncontrolled. So if you're not doing the stitching appropriately, if you're not cleaning up these polygon layers appropriately, if you're letting the polygon pors get too close to your controlled impedance traces and so on, you can actually mess things up. So often times a guideline is to simply on these outer layers or these signal **[23:16](https://youtu.be/Ao2HUjjhlmQ?t=1396)** layers to not pour any copper. However, arguments against that are copper balancing. So if we have uneven copper distribution between layers, so across the Z axis or even in parts along the XY plane, if we have uneven copper distribution, that can lead to manufacturing risk because the copper and the actual dialectric material, the fiberglass, they have different coefficients of thermal expansion. So during manufacturing, during pressing, also during assembly, the different materials in your printed circuit board will expand at different rates. But by **[23:49](https://youtu.be/Ao2HUjjhlmQ?t=1429)** keeping the copper distribution even and balanced across the boards in all axes and along all axes, we can somewhat mitigate this warping and bending of the board during manufacturing. Now although quite exaggerated copper balance issues can lead to increased bow and twist of the boards. Now all these pictures are somewhat exaggerated. Maybe not this one. You can see there's quite a bit of arching in the board and that can of course lead to reliability issues where you get cracking in the copper itself and of course issues with assembly. If you need a certain planarity, a certain **[24:21](https://youtu.be/Ao2HUjjhlmQ?t=1461)** flatness of your printed circuit board. So that's why copper balance is important. Now if you don't want to do that, I'd suggest talking to your manufacturer and talk about if your board is manufacturable as such without these copper paws on the signal layers and without copper balancing. Often times manufacturers will also add in copper thieving themselves, but it's something you should really discuss with your manufacturer. On that topic, I'd really strongly suggest watching the secrets of PCB optimization video by Rick Hartley, which goes into more detail on copper balancing and why that is needed. These days, I typically pour crop on all layers, but that does mean it takes me quite a lot of time to just clean up these polygon PS, make sure the **[24:54](https://youtu.be/Ao2HUjjhlmQ?t=1494)** stitching is appropriate, make sure I've kept my polygon pors away from all sensitive circuitry such as controlled impedance traces and so on. But that is my personal approach and it depends on board to board. There is no generic blanket statement for this. If you do have unstitched areas, again you can use these polygon pore cutouts, but you can also go to the polygon properties itself and check the remove islands section. Always I would suggest check the remove dead copper section. Lastly, just for the sake of completeness, you might have heard of hatched and solid fills typically for rigid printed solid fills **[25:28](https://youtu.be/Ao2HUjjhlmQ?t=1528)** is what you would use here. And as we can see here, the option for hatched is available pretty much in any e-cat tool. If we go to the properties, click on hatched, we can see it looks hatched. There are different hatching methods. So, horizontal, we can do vertical, 45° and 90° and so on. And this is, at least in my opinion, predominantly just used in flexible printed circuit boards where along the bend line of the flexible printed circuit board, you might want to use a hatch plane to reduce the risk of cracking and to make the board easier to bend along that certain bend line. for **[26:03](https://youtu.be/Ao2HUjjhlmQ?t=1563)** so for rigid PCBs, I would pretty much always just use solid copper fills. But then for flex PCBs or rigid flex PCBs, you typically want to use these hatched copper fills again to try and avoid cracking during bending and improve the mechanical flexibility of your flex printed circuit board. So again, just stick with solid for your rigid PCBs. Thank you very much for watching this video. I hope it was useful and I hope it showed you the basics of what to pay attention to when using copper balls and copper fills on your own printed circuit board designs. If you like the video, **[26:35](https://youtu.be/Ao2HUjjhlmQ?t=1595)** please leave a like, a comment if you have any questions, and don't forget to subscribe to stay up to date with any latest PCB design, hardware design, and embedded systems videos. Thanks again for watching, and I hope to see you in the next one. Bye-bye.