#pcb #layout #emi #electronics #predictable-designs #youtube # Overview Distillation of John Teel's (Predictable Designs) *11 PCB Layout Rules to NEVER Break* (12 min, 2026-09-03). His framing: two boards from the same schematic can behave completely differently — one passes, the other fails EMI, resets randomly, or has no wireless range — because layout is where the physics happens. [0:00](https://youtu.be/juOTCCq_eig?t=0) Background: over a decade as a microchip design engineer at Texas Instruments, then launched his own product, now runs a hardware academy. [0:34](https://youtu.be/juOTCCq_eig?t=34) The video counts down from 11 to 1, ending with the rule he calls the most invisible and most expensive to fix. [0:20](https://youtu.be/juOTCCq_eig?t=20) This note regroups the rules by theme (**Assembly & Fab** → **Power** → **Signal Integrity & EMI** → **RF**); the countdown table below keeps his order. Every bullet links to the moment it's said. # Resources - [Video](https://www.youtube.com/watch?v=juOTCCq_eig) · full timestamped transcript: [[Predictable Designs PCB Layout Rules Transcript]] - [PCB Layout Rules Checklist](https://predictabledesigns.com/pcb-layout-rules-checklist/) — his free checklist covering every rule; run through it before ordering boards [1:47](https://youtu.be/juOTCCq_eig?t=107) - Related: [[KiCad Design Tips]] · [[JLCPCB Design Notes]] · [[KiCad 9 MCU Board Design Workflow]] (Phil's Lab applies several of these rules hands-on in KiCad) # The 11 Rules | # | Never… | Do instead | Video | |---|---|---|---| | 11 | Use via-in-pad without knowing the cost | Vias next to the pad + short trace; if unavoidable, spec filled & capped vias and budget for it | [0:48](https://youtu.be/juOTCCq_eig?t=48) | | 10 | Design a board without test points | Pads on every power rail, every comm bus, anything for programming/debug | [1:55](https://youtu.be/juOTCCq_eig?t=115) | | 9 | Skip a thermal path for hot components | Datasheet landing pattern incl. thermal via array; max copper area | [2:55](https://youtu.be/juOTCCq_eig?t=175) | | 8 | Run high-speed traces near the board edge | ≥4–5× trace-to-plane height from edge (~1 mm+); inner layers | [4:10](https://youtu.be/juOTCCq_eig?t=250) | | 7 | Leave the board without stitching vias | Ground stitching everywhere — edges, high-speed routing, RF | [5:03](https://youtu.be/juOTCCq_eig?t=303) | | 6 | Ignore the switching regulator hot loop | Input cap as close as possible; single layer; copy the datasheet layout | [5:58](https://youtu.be/juOTCCq_eig?t=358) | | 5 | Route differential pairs like ordinary traces | Length match, controlled impedance, unbroken reference plane, no stubs; use the tool's diff-pair router | [6:42](https://youtu.be/juOTCCq_eig?t=402) | | 4 | Starve a power trace or via | Size for worst-case current with margin; pours for high current; parallel vias at layer changes | [7:33](https://youtu.be/juOTCCq_eig?t=453) | | 3 | Put copper under an antenna | Honor the datasheet keep-out on all layers, incl. screws/standoffs | [8:30](https://youtu.be/juOTCCq_eig?t=510) | | 2 | Place decoupling capacitors far from the pin | Cap at the pin, short wide trace, ground vias at the cap pad | [9:40](https://youtu.be/juOTCCq_eig?t=580) | | 1 | Route signals across a plane split | Check every trace against the planes beneath it on every layer; reroute anything crossing a gap | [10:32](https://youtu.be/juOTCCq_eig?t=632) | # Assembly and Fab ## Via-in-pad (Rule 11) - Via-in-pad = a via placed directly inside a component's solder pad instead of next to it. Tempting because it saves space, and for fine-pitch BGAs it's sometimes the only option. [0:48](https://youtu.be/juOTCCq_eig?t=48) - Cost 1 — assembly: molten solder wicks down the open via "like a straw", starving the joint → weak or open connection. [1:07](https://youtu.be/juOTCCq_eig?t=67) - Cost 2 — fab: the fix is having the fab epoxy-fill each via and plate copper over the top, which adds real money to every board you ever build. [1:20](https://youtu.be/juOTCCq_eig?t=80) - Unless you truly need it, place vias next to the pad and connect with a short trace. [1:32](https://youtu.be/juOTCCq_eig?t=92) - If you do need it, specify **filled and capped vias** in the fab notes and budget for the extra cost from day one. [1:40](https://youtu.be/juOTCCq_eig?t=100) - The exception: thermal vias in a power pad are technically via-in-pad, but that's the one place it's normally acceptable — solder wicking there mostly causes small voids rather than failed connections. [3:30](https://youtu.be/juOTCCq_eig?t=210) ## Test points (Rule 10) - A board with no test points can't be tested in production: you either ship unverified units or pay someone to probe every board by hand. [1:55](https://youtu.be/juOTCCq_eig?t=115) - Factories test with a fixture of spring-loaded pogo pins that need dedicated copper pads to land on; adding them later means a new board revision. [2:13](https://youtu.be/juOTCCq_eig?t=133) - Test points are basically free — small exposed copper circles on signals and power rails. [2:30](https://youtu.be/juOTCCq_eig?t=150) - Add them to every power rail, every communication bus, and anything needed for programming or debugging. [2:38](https://youtu.be/juOTCCq_eig?t=158) - Also a lifesaver when debugging leadless packages (QFN, BGA) where the pins are hidden under the chip and there's nothing to probe. [2:46](https://youtu.be/juOTCCq_eig?t=166) ## Thermal path (Rule 9) - A regulator that works for 10 minutes then browns out is commonly a layout problem and not necessarily a component problem. [2:58](https://youtu.be/juOTCCq_eig?t=178) - Many regulators and hot parts dissipate heat through an exposed bottom pad (power pad), which needs an array of thermal vias down to a large copper pour on another layer. [3:12](https://youtu.be/juOTCCq_eig?t=192) - Skip the vias and heat piles up until thermal shutdown → the product resets over and over in the field. [3:45](https://youtu.be/juOTCCq_eig?t=225) - Follow the datasheet landing pattern exactly, including the recommended via array, and give the part as much copper area as you can spare — "copper is free" and it's the cheapest heat sink you'll get. [3:55](https://youtu.be/juOTCCq_eig?t=235) # Power ## Power trace and via sizing (Rule 4) - A too-thin power trace drops voltage under load, heats up, and in the worst case burns off the board. [7:38](https://youtu.be/juOTCCq_eig?t=458) - Same for vias — a single small via might only handle an amp or so before it's the bottleneck. [7:45](https://youtu.be/juOTCCq_eig?t=465) - Common failure mode: power routed at the default signal trace width; fine at low current in early testing, then the rail sags under high load and the MCU resets at the worst moment. [7:52](https://youtu.be/juOTCCq_eig?t=472) - Trace width calculators are free and take seconds; size every power trace for its actual current under worst-case conditions with plenty of margin. [8:08](https://youtu.be/juOTCCq_eig?t=488) - For higher currents use copper pours instead of traces, and always place multiple vias in parallel wherever power changes layers. [8:20](https://youtu.be/juOTCCq_eig?t=500) ## Decoupling capacitors (Rule 2) - A decoupling cap is a tiny local energy tank that feeds the chip during sudden current spikes faster than the main supply can respond. [9:48](https://youtu.be/juOTCCq_eig?t=588) - Every millimeter of trace between cap and pin adds inductance, which resists exactly those fast current changes; too far away and you've built a filter that blocks the cap from doing its one job → supply dips → random glitches and resets. [9:59](https://youtu.be/juOTCCq_eig?t=599) - Place the cap close to the pin, connect with a short wide trace, and drop ground vias right at the capacitor's pad. [10:15](https://youtu.be/juOTCCq_eig?t=615) ## Switching regulator hot loop (Rule 6) - The hot loop is the current path where current starts and stops in a few nanoseconds; it behaves like a tiny transmitting antenna, and the bigger the loop area the more noise it sprays across the board. [6:05](https://youtu.be/juOTCCq_eig?t=365) - TI and Analog Devices publish recommended layouts in their switching regulator datasheets specifically to keep this loop tiny. [6:20](https://youtu.be/juOTCCq_eig?t=380) - Place the input capacitor as close to the regulator as physically possible, keep the loop on a single layer, and copy the datasheet layout instead of improvising. [6:30](https://youtu.be/juOTCCq_eig?t=390) # Signal Integrity and EMI ## High-speed traces near the board edge (Rule 8) - Near the edge, the electric field around a trace is no longer fully contained between trace and ground plane; the fringing field radiates like a little antenna. [4:15](https://youtu.be/juOTCCq_eig?t=255) - Looks fine on the bench; the test lab's antennas pick it up immediately, and every failed EMI scan costs money and weeks of schedule. [4:32](https://youtu.be/juOTCCq_eig?t=272) - Keep fast signals (clocks, USB, memory buses) at least **4–5× the trace-to-ground-plane distance** from the edge — on most boards around **1 mm or more**. [4:45](https://youtu.be/juOTCCq_eig?t=285) - Route on inner layers whenever possible. [4:58](https://youtu.be/juOTCCq_eig?t=298) ## Stitching vias (Rule 7) - Stitching vias are rows of ground vias tying ground planes together across the board. Without them, ground currents on different layers can't take the shortest path back, and gaps between planes act like slots that leak radiation. [5:03](https://youtu.be/juOTCCq_eig?t=303) - Along the board edges they form a fence that helps contain noise inside the board. [5:22](https://youtu.be/juOTCCq_eig?t=322) - Anecdote: a board he reviewed looked clean everywhere else but had no stitching vias; caught right before the fab order. Adding them cost nothing and meaningfully improves the odds of passing FCC testing first try. [5:28](https://youtu.be/juOTCCq_eig?t=328) - Sprinkle ground stitching vias everywhere possible — especially along edges, around high-speed routing, and around RF circuits or antenna feed lines. [5:45](https://youtu.be/juOTCCq_eig?t=345) ## Differential pairs (Rule 5) - USB, Ethernet, HDMI carry equal and opposite signals; the receiver only reads the difference, so interference hitting both traces cancels — but only when the layout is right. [6:48](https://youtu.be/juOTCCq_eig?t=408) - Requirements: length matched, controlled impedance, an unbroken reference plane underneath, and no stubs on either line. [7:11](https://youtu.be/juOTCCq_eig?t=431) - Get any of those wrong and signals arrive skewed or reflected → random errors that are brutal to debug. [7:20](https://youtu.be/juOTCCq_eig?t=440) - Your PCB software has built-in differential-pair routing tools — use them. [7:28](https://youtu.be/juOTCCq_eig?t=448) ## Plane splits (Rule 1) - Routing a signal across a split in a ground or power plane is the most invisible and most expensive mistake on the list. [10:32](https://youtu.be/juOTCCq_eig?t=632) - At high frequencies the return current flows in the plane directly under the trace; at a split it can't follow, so it detours around the gap, creating a huge loop that radiates noise. [10:45](https://youtu.be/juOTCCq_eig?t=645) - Couples interference into every nearby circuit; a leading cause of both EMI failures and mystery glitches nobody can reproduce. [11:06](https://youtu.be/juOTCCq_eig?t=666) - Nothing looks wrong — the trace appears normal and every net checks out in the design software. [11:12](https://youtu.be/juOTCCq_eig?t=672) - Plane splits themselves are sometimes the right choice (e.g. isolating a sensitive analog section); the rule is about what you route over them. [11:20](https://youtu.be/juOTCCq_eig?t=680) - Before ordering, check every trace against the planes beneath it on every layer and reroute anything that crosses a gap. [11:30](https://youtu.be/juOTCCq_eig?t=690) # RF ## Antenna keep-out (Rule 3) - Copper under an antenna kills wireless range: an antenna couples energy into the space around it, and a ground plane or any copper under or near it detunes it and absorbs the energy. [8:35](https://youtu.be/juOTCCq_eig?t=515) - Every antenna and pre-certified wireless module has a keep-out zone in its datasheet — no copper traces or components on **any** layer. [8:53](https://youtu.be/juOTCCq_eig?t=533) - Same for metal mounting screws and standoffs — metal that close detunes it just like copper. [9:05](https://youtu.be/juOTCCq_eig?t=545) - Certification angle: a pre-certified module is only certified when used the way the datasheet specifies; violate the keep-out and it no longer performs as certified, which can bite during compliance testing. [9:15](https://youtu.be/juOTCCq_eig?t=555) - Look at any wireless module dev board — the bare region around the antenna is what your layout should have too. [9:32](https://youtu.be/juOTCCq_eig?t=572) # References - [[Predictable Designs PCB Layout Rules Transcript]] - [[KiCad 9 MCU Board Design Workflow]] — Phil's Lab applies decoupling placement and stitching vias in practice - [[JLCPCB Design Notes]] — where filled/capped via options are chosen at order time