#pcb #layout #signal-integrity #electronics #phils-lab #youtube # Overview Distillation of Phil Salmony's (Phil's Lab) *How To Improve Your PCB Designs (Common Mistakes)* (#18, 9:26, uploaded 2021-01-18, sponsored by JLCPCB). He walks through the mistakes he most often sees in PCB designs people share, and how to fix them for better signal integrity and EMI. [0:00](https://youtu.be/IclJ9nbtYgI?t=0) The example is a mixed-signal board (6-layer per the description) that was to be the project for his upcoming PCB design course. [0:55](https://youtu.be/IclJ9nbtYgI?t=55) The demo tool appears to be KiCad (captioned "keycap"). [2:05](https://youtu.be/IclJ9nbtYgI?t=125) This is an early (2021) video; several points come back in more depth in [[PCB Copper Pours 101]] (#176). Every bullet links to the moment it's said. ## The five topics | # | Topic | What he does / recommends | Video | |---|---|---|---| | 1 | Trace width | His default: signals at a 50 Ω controlled-impedance width; power traces sized for current; stay off fab minimums | [1:38](https://youtu.be/IclJ9nbtYgI?t=98) | | 2 | Clearance | Mistake he often sees: traces with virtually no space between them. Space them ≥3× trace width; keep analog and digital sections apart | [3:18](https://youtu.be/IclJ9nbtYgI?t=198) | | 3 | Via placement | Decoupling via as close to the pad as possible (not in it), wide trace, power/GND via pairs close together | [5:21](https://youtu.be/IclJ9nbtYgI?t=321) | | 4 | Copper fills | Solid, continuous GND plane; split power planes only where no adjacent-layer signal crosses the split | [7:07](https://youtu.be/IclJ9nbtYgI?t=427) | | 5 | Silkscreen | Mistake he sees a lot: designators on pads. Keep silk off pads and mostly off vias; never move parts to suit silk | [8:32](https://youtu.be/IclJ9nbtYgI?t=512) | # Resources - [Video](https://www.youtube.com/watch?v=IclJ9nbtYgI) · full timestamped transcript: [[Phil's Lab 18 Transcript]] - [Saturn PCB Design Toolkit](https://saturnpcb.com/pcb_toolkit/) — free calculator he often uses: impedance for controlled-impedance traces, crosstalk, differential pairs, and conductor current capacity. He recommends downloading it. [1:15](https://youtu.be/IclJ9nbtYgI?t=75) [2:09](https://youtu.be/IclJ9nbtYgI?t=129) ==Not from the video: as far as I know it's a Windows-only app — check before relying on it on macOS.== - [Rick Hartley — How to Achieve Proper Grounding](https://www.youtube.com/watch?v=ySuUZEjARPY) — a talk Hartley gave at an Altium event, on Altium's YouTube channel; Phil calls it possibly the best PCB design video he has ever watched and says the 2 h 20 min is well worth your time. [6:40](https://youtu.be/IclJ9nbtYgI?t=400) - His reference designs (Gerbers + assembly files), including STM32F4/STM32F1 breakout boards: [github.com/pms67](https://github.com/pms67) [0:32](https://youtu.be/IclJ9nbtYgI?t=32) - Related: [[PCB Copper Pours 101]] · [[PCB Layout Rules to Never Break]] · [[KiCad 9 MCU Board Design Workflow]] · [[JLCPCB Design Notes]] # 1 — Trace Width - The example board uses a range of widths: very thick traces in the power section, thinner ones for signals. [1:38](https://youtu.be/IclJ9nbtYgI?t=98) - His habit for signal traces: route them as **50 Ω controlled-impedance traces** by default; if something needs a different impedance (60 Ω, 45 Ω), route that instead. [1:50](https://youtu.be/IclJ9nbtYgI?t=110) - He sets up a 50 Ω track width in the ECAD tool up front and generally starts his signal traces with it. [2:05](https://youtu.be/IclJ9nbtYgI?t=125) - Higher currents → wider traces. Saturn toolkit → *Conductor Properties*: for a given conductor width and copper thickness, it gives the current capacity for a given temperature rise. [2:09](https://youtu.be/IclJ9nbtYgI?t=129) - The power section uses wide traces (he starts to say copper pours, then corrects himself); signal traces carry virtually no current, so they can be much thinner. [2:35](https://youtu.be/IclJ9nbtYgI?t=155) - Every fab has a capabilities page listing minimum trace width and spacing. His recommendation: always try to stay away from the minimum trace width — even if the fab can do **3.5 mil / 0.09 mm**, don't stress their manufacturing capabilities. [2:50](https://youtu.be/IclJ9nbtYgI?t=170) [3:00](https://youtu.be/IclJ9nbtYgI?t=180) # 2 — Clearance - Common mistake: designs with virtually no space between traces. This hurts signal integrity, predominantly through crosstalk. [3:18](https://youtu.be/IclJ9nbtYgI?t=198) - The Saturn toolkit's crosstalk calculator shows how much voltage couples between traces for a given spacing — it can be really significant and cause problems in both digital and analog systems. [3:30](https://youtu.be/IclJ9nbtYgI?t=210) [3:49](https://youtu.be/IclJ9nbtYgI?t=229) - A typical rule: space traces **at least three times the trace width** apart (3W) — much less crosstalk than running them right next to each other. [3:58](https://youtu.be/IclJ9nbtYgI?t=238) - Routing habit (I²C example): turn the trace away as soon as it leaves the pad, so space opens up between neighbouring traces immediately instead of leaving parallel sections running side by side. [4:22](https://youtu.be/IclJ9nbtYgI?t=262) - Clearance applies to components and circuit sections too: on this mixed-signal board he keeps the digital and power sections as far from the analog section as he can. [4:45](https://youtu.be/IclJ9nbtYgI?t=285) - It's "pretty much all about the space": as much as you can get between traces and between sections (analog vs digital) — "if you have the space use it". [5:05](https://youtu.be/IclJ9nbtYgI?t=305) # 3 — Via Placement - This board (he says it's four- or six-layer) has internal GND and 3.3 V planes, so parts that need power or ground (e.g. capacitors) just "dig down" into them with vias. [5:28](https://youtu.be/IclJ9nbtYgI?t=328) - Bypass/decoupling caps sit close to the main signal-processing chip / MCU. [5:40](https://youtu.be/IclJ9nbtYgI?t=340) - The via goes **as close to the pad as possible without being in the pad**, connected by a very wide trace into the pad → minimum inductance. [5:45](https://youtu.be/IclJ9nbtYgI?t=345) [5:58](https://youtu.be/IclJ9nbtYgI?t=358) - Vias typically come in pairs: a signal via with a ground via, or a power (3.3 V) via with a ground via. [6:05](https://youtu.be/IclJ9nbtYgI?t=365) - To minimise inductance, it's not enough to use thick traces and keep vias near the pads — keep each via pair (e.g. GND and 3.3 V) close to each other too. [6:15](https://youtu.be/IclJ9nbtYgI?t=375) - All the bypass/decoupling caps on the board follow this pattern. [6:34](https://youtu.be/IclJ9nbtYgI?t=394) # 4 — Copper Fills and Planes - In a multilayer board, internal layers are typically filled with ground, VCC, etc., depending on the stackup. [7:07](https://youtu.be/IclJ9nbtYgI?t=427) - His main ground plane is solid and continuous — not split, even though the board is mixed-signal. "In pretty much 99.9 percent of all cases you shouldn't split your ground plane." [7:20](https://youtu.be/IclJ9nbtYgI?t=440) [7:30](https://youtu.be/IclJ9nbtYgI?t=450) - With analog and digital domains, the most important thing is the **spacing** between the analog and digital sections — that's what reduces crosstalk. In most scenarios there's no point in a split ground plane; there are exceptions. [7:38](https://youtu.be/IclJ9nbtYgI?t=458) - Power planes are different: his power layer is split into sections by voltage — 3.3 V digital, 9 V analog, and an analog 3.3 V. [7:55](https://youtu.be/IclJ9nbtYgI?t=475) [8:10](https://youtu.be/IclJ9nbtYgI?t=490) - Splitting power is OK **only if** no signals on the directly adjacent layer cross the splits. Here the next layer is a signal layer and nothing runs across the gaps. [8:10](https://youtu.be/IclJ9nbtYgI?t=490) # 5 — Silkscreen - A very small and minor detail, but he thinks it's important for getting boards produced correctly. [8:32](https://youtu.be/IclJ9nbtYgI?t=512) - Common mistake: designators placed on pads — they won't print and the silkscreen gets cut off. Don't put silkscreen on pads. [8:43](https://youtu.be/IclJ9nbtYgI?t=523) - Try not to put silkscreen on holes or vias. Tented vias (covered in solder mask) can usually take silkscreen, but it won't look as nice; he moves text so it's only barely on a via, which prints better than directly over the hole. [8:55](https://youtu.be/IclJ9nbtYgI?t=535) - Never sacrifice component placement for silkscreen placement — silkscreen is a guide; component placement is more important. [9:16](https://youtu.be/IclJ9nbtYgI?t=556) # References - [[Phil's Lab 18 Transcript]] — raw timestamped transcript this note was distilled from - [[PCB Copper Pours 101]] — Phil's Lab #176: pour clearances, the same fab-minimum advice (JLC 0.09 mm multilayer), stitching and copper balance - [[PCB Layout Rules to Never Break]] — Predictable Designs; Rule 1 (never route across plane splits) and Rule 2 (decoupling at the pin) match points 4 and 3 here - [[KiCad 9 MCU Board Design Workflow]] — Phil's Lab #165/166: decoupling placement and trace widths applied in KiCad 9 - [[JLCPCB Design Notes]] — JLC capabilities page # Changelog ## 2026-09-24 - Note created from Phil's Lab #18 (auto-captions via yt-dlp); companion transcript saved as [[Phil's Lab 18 Transcript]].