#pcb #layout #copper-pour #thermal-relief #electronics #phils-lab #youtube # Overview Distillation of Phil Salmony's (Phil's Lab) *PCB Copper Pours 101* (#176, 26:47, uploaded 2026-07-31): the basics of copper pours, polygon pours, fills and planelets — when to use them, when not to, and how to keep them from causing problems. [0:00](https://youtu.be/Ao2HUjjhlmQ?t=0) A copper pour is a polygon fill that floods part of the board with copper and is assigned to a net; it's very similar to a trace but serves different purposes and is usually much larger. [0:17](https://youtu.be/Ao2HUjjhlmQ?t=17) His framing: pours "should never be used simply for decorative reasons" — every fill on the board has a reason for being there. [2:10](https://youtu.be/Ao2HUjjhlmQ?t=130) The demo is in Altium Designer on a 4-layer digital audio processing board, but he notes any ECAD tool has the same sets of rules. [2:57](https://youtu.be/Ao2HUjjhlmQ?t=177) [5:00](https://youtu.be/Ao2HUjjhlmQ?t=300) This note is grouped by topic, loosely following his chapters; every bullet links to the moment it's said. A KiCad mapping (not from the video) is at the end. What pours are for: - Board-spanning pours (e.g. the top-layer GND pour), smaller pours over a subsection used as higher-current "traces", and reference planes on internal layers. [0:33](https://youtu.be/Ao2HUjjhlmQ?t=33) - On this 4-layer board, L2 and L3 are board-spanning pours, each tied to its own net — often GND / 0 V. [1:02](https://youtu.be/Ao2HUjjhlmQ?t=62) - A solid reference pour on the layer next to L1 traces gives a low-impedance return path, which helps EMI and signal integrity. [1:10](https://youtu.be/Ao2HUjjhlmQ?t=70) - Beyond return paths: heat sinking, thermal spreading, balancing copper across layers, and power distribution. [1:39](https://youtu.be/Ao2HUjjhlmQ?t=99) ## Cheat sheet | Topic | His default / guideline | Video | |---|---|---| | Clearances & widths | Take the fab's capability numbers, add margin; use minimums only locally | [6:50](https://youtu.be/Ao2HUjjhlmQ?t=410) | | Neck-downs | Only when you really have to; widen again wherever there's space | [7:55](https://youtu.be/Ao2HUjjhlmQ?t=475) | | Pour order | Small pours first, the big GND pour last | [11:06](https://youtu.be/Ao2HUjjhlmQ?t=666) | | Pads on large GND pours | Thermal relief — a "very very general guideline" | [15:25](https://youtu.be/Ao2HUjjhlmQ?t=925) | | Vias | Direct connect, as a complete default | [17:13](https://youtu.be/Ao2HUjjhlmQ?t=1033) | | Spoke width | 60 % of pad side ÷ number of spokes | [16:30](https://youtu.be/Ao2HUjjhlmQ?t=990) | | Stitching-via spacing | λ/8; λ/20 if very strict | [21:36](https://youtu.be/Ao2HUjjhlmQ?t=1296) | | Pour outer layers? | He now typically pours all layers, but it's a board-by-board call | [24:45](https://youtu.be/Ao2HUjjhlmQ?t=1485) | | Dead copper | Always tick *Remove Dead Copper* | [25:10](https://youtu.be/Ao2HUjjhlmQ?t=1510) | | Fill style | Solid on rigid boards; hatched for flex / rigid-flex (along bend lines) | [26:03](https://youtu.be/Ao2HUjjhlmQ?t=1563) | # Resources - [Video](https://www.youtube.com/watch?v=Ao2HUjjhlmQ) · full timestamped transcript: [[Phil's Lab 176 Transcript]] - Links from the description: - [PCB Stack-Up and Build-Up](https://www.youtube.com/watch?v=QAOEtfvCaMw) — his video #56, for stackups and when to use pours as reference planes; also a summary article on resources.altium.com [1:50](https://youtu.be/Ao2HUjjhlmQ?t=110) - [PCB Design Rules 101](https://www.youtube.com/watch?v=zeH3WbMWvdg) — his video #170, on setting up design rules and applying them locally vs globally [5:32](https://youtu.be/Ao2HUjjhlmQ?t=332) - [Rick Hartley & Robert Feranec video](https://www.youtube.com/watch?v=52fxuRGifLU) — deeper dive on layer ordering, pouring and stackup [2:30](https://youtu.be/Ao2HUjjhlmQ?t=150) - [Secrets of PCB Optimisation](https://www.youtube.com/watch?v=0RyBCnowLsI) — Altium Academy, with Rick Hartley; DFM, and copper balancing in more detail [2:45](https://youtu.be/Ao2HUjjhlmQ?t=165) [24:40](https://youtu.be/Ao2HUjjhlmQ?t=1480) - [Thermal Relief Design Guide](https://resources.altium.com/p/thermal-relief-design) — Altium resources (listed in description, not discussed on camera) - His previous video on via fencing and edge plating covers stitching in more detail (not linked in the description). [20:10](https://youtu.be/Ao2HUjjhlmQ?t=1210) - IPC-2221 and IPC-2222 for thermal-relief spoke sizing details. [16:55](https://youtu.be/Ao2HUjjhlmQ?t=1015) - Related: [[KiCad 9 MCU Board Design Workflow]] (Phil's Lab #165/166 — the same ideas applied in KiCad) · [[PCB Layout Rules to Never Break]] · [[JLCPCB Design Notes]] · [[KiCad Design Tips]] # Design Rules Pours on any layer obey design rules just like traces, pads and components: the goal is a manufacturable board, minimal (ideally no) assembly issues, and pours that help EMI and signal integrity. [4:02](https://youtu.be/Ao2HUjjhlmQ?t=242) For manufacturability, the big one is clearance. [4:40](https://youtu.be/Ao2HUjjhlmQ?t=280) ## Values shown in the demo | Rule | Value | Context | Video | |---|---|---|---| | Polygon-to-polygon clearance | ~0.35 mm | Small 3.3 V pour | [4:40](https://youtu.be/Ao2HUjjhlmQ?t=280) | | Pour neck width | ~0.45 mm | 1.2 V distribution pour necking down between parts | [7:46](https://youtu.be/Ao2HUjjhlmQ?t=466) | | *Remove Necks Less Than* (Obey rules unticked) | 0.6 mm — ==caption says "6 mm"; 0.6 fits the demo, verify== | Repour → the ~0.45 mm neck disconnects | [8:35](https://youtu.be/Ao2HUjjhlmQ?t=515) | | *Remove Islands Less Than* | 5 — ==caption unit garbled ("square meters"); check units on screen== | Adjustable | [9:35](https://youtu.be/Ao2HUjjhlmQ?t=575) | | JLCPCB min trace width / spacing | 0.1 mm (1–2 layers) · 0.09 mm (multilayer, >2) | Absolute fab minimums — stay away if your design allows; use only locally where needed | [6:38](https://youtu.be/Ao2HUjjhlmQ?t=398) | ## Clearance - Clearance applies pour-to-pour, pour-to-SMD pad, pour-to-trace, and to features within the same net. [4:59](https://youtu.be/Ao2HUjjhlmQ?t=299) - Altium: Design Rules → Clearance has a copper row: copper-to-track, -SMD pad, -TH pad, -via, -copper, and copper-to-hole. Set them responsibly for your constraints and manufacturer. [5:10](https://youtu.be/Ao2HUjjhlmQ?t=310) - Design for a large group of manufacturers, not just one, and without going near minimums — the aim is reliable manufacture with high yield (most boards come out without defects). [5:45](https://youtu.be/Ao2HUjjhlmQ?t=345) - Pull numbers from your fab's capabilities page. Pour rules may sit under the traces section because traces and pours share the same clearance constraints. [6:05](https://youtu.be/Ao2HUjjhlmQ?t=365) - He "strongly" suggests staying away from the fab minimums; if you have to use them, apply them only locally where needed and always add margin. [6:50](https://youtu.be/Ao2HUjjhlmQ?t=410) [7:11](https://youtu.be/Ao2HUjjhlmQ?t=431) - Also consider same-net track-to-track spacing and via-hole-to-copper clearance; transfer everything to the ECAD tool with margin. [7:11](https://youtu.be/Ao2HUjjhlmQ?t=431) - Why the rules exist: features too close risk shorts from manufacturing tolerances. [9:00](https://youtu.be/Ao2HUjjhlmQ?t=540) - High-voltage designs: account for creepage and clearance requirements → larger clearances between nets. [9:15](https://youtu.be/Ao2HUjjhlmQ?t=555) ## Minimum width and necks - Minimum width matters for pours too — the same kind of rule as minimum trace width. [7:38](https://youtu.be/Ao2HUjjhlmQ?t=458) [8:19](https://youtu.be/Ao2HUjjhlmQ?t=499) - Only neck a current-carrying or power pour down when you really need to; don't keep it narrower than necessary, and widen it wherever there's space. Even when necking, stay above the minimum. [7:55](https://youtu.be/Ao2HUjjhlmQ?t=475) - Necks that are too narrow may not connect properly or may break. [9:00](https://youtu.be/Ao2HUjjhlmQ?t=540) - You need both clearance rules and minimum pour-width rules. [8:52](https://youtu.be/Ao2HUjjhlmQ?t=532) ## Islands - *Remove Islands Less Than* is useful for polygon cleanup — e.g. removing small islands that aren't, or can't be, stitched properly. [9:35](https://youtu.be/Ao2HUjjhlmQ?t=575) [9:40](https://youtu.be/Ao2HUjjhlmQ?t=580) ## Per-layer rules - Rules can differ per layer: inner layers (L2/L3) will likely have different constraints from the outer layers. [10:01](https://youtu.be/Ao2HUjjhlmQ?t=601) - Keep pours further from controlled-impedance traces (here USB 2.0 and USB 3 SuperSpeed differential pairs) — bringing planelets closer throws off the impedance you calculated. [10:10](https://youtu.be/Ao2HUjjhlmQ?t=610) - He gives L1/L4 slightly different clearances from the inner layers, partly for the controlled-impedance traces and partly because the top and bottom carry many small pours and planelets. [10:40](https://youtu.be/Ao2HUjjhlmQ?t=640) # Pour Order (Priority) - Pour order matters. On L1 he pours all the smaller polygons first and the GND pour (which covers essentially the whole top and bottom) last. [10:58](https://youtu.be/Ao2HUjjhlmQ?t=658) [11:06](https://youtu.be/Ao2HUjjhlmQ?t=666) - Altium: Tools → Polygon Pours → Polygon Manager sets the pour order — smaller nets first, GND last. [11:15](https://youtu.be/Ao2HUjjhlmQ?t=675) - Demo: move GND earlier and Repour All → GND takes priority and the VBUS pour doesn't pour correctly. [11:30](https://youtu.be/Ao2HUjjhlmQ?t=690) # Thermal Relief vs Direct Connect - **Direct connect**: the pour flows over every feature inside its area — pads, vias and so on. [11:49](https://youtu.be/Ao2HUjjhlmQ?t=709) [12:00](https://youtu.be/Ao2HUjjhlmQ?t=720) - **Thermal relief**: small spokes join the pour to the pad at suitable points instead of covering it — e.g. the GND pads of a 0603 capacitor. [12:25](https://youtu.be/Ao2HUjjhlmQ?t=745) ## Trade-offs | | Direct connect | Thermal relief | |---|---|---| | Connection | Full connection to the pad; better thermal conductivity [12:47](https://youtu.be/Ao2HUjjhlmQ?t=767) | Spokes only | | Inductance | Lower | Higher — matters for decoupling and power delivery [14:25](https://youtu.be/Ao2HUjjhlmQ?t=865) | | Soldering | Big thermal mass on one pad → uneven heating, tombstoning [13:30](https://youtu.be/Ao2HUjjhlmQ?t=810) [13:52](https://youtu.be/Ao2HUjjhlmQ?t=832) | Evens out heating; easier hand soldering of TH parts [14:57](https://youtu.be/Ao2HUjjhlmQ?t=897) | - Direct connect would typically be preferred were it not for its manufacturability issues (==caption garbled here — context reads as "if it weren't for"==). [12:47](https://youtu.be/Ao2HUjjhlmQ?t=767) - The problem is copper imbalance: a large GND pour is a big thermal mass on one side of a small part while the other pad has little copper, so the GND pad acts as a heat sink and heats more slowly than the other. [13:00](https://youtu.be/Ao2HUjjhlmQ?t=780) [13:30](https://youtu.be/Ao2HUjjhlmQ?t=810) - How much this matters depends on the soldering method (iron, reflow profile, etc.). [13:30](https://youtu.be/Ao2HUjjhlmQ?t=810) - For small SMD parts this can cause tombstoning — the part stands up on one end, a significant manufacturing defect. [13:52](https://youtu.be/Ao2HUjjhlmQ?t=832) - So, depending on how big the copper imbalance is either side of the part, typically add thermal reliefs. [14:10](https://youtu.be/Ao2HUjjhlmQ?t=850) - Through-hole: a TH pad that'll be wave soldered or hand soldered, solidly connected to GND pours on all four layers, would be very difficult to solder, especially by hand; reliefs help for wave soldering too. [14:40](https://youtu.be/Ao2HUjjhlmQ?t=880) [14:57](https://youtu.be/Ao2HUjjhlmQ?t=897) - Always a trade-off between thermals, inductance and solderability/manufacturability. Ask: what is this pin connected to, what are the other pins connected to, is there thermal or copper imbalance? [15:08](https://youtu.be/Ao2HUjjhlmQ?t=908) - His "very very general guideline": use thermal reliefs, especially with large GND pours on the top and bottom layers and large imbalances between a component's sides. Also applies to multi-pin parts — check copper balance and how the board is assembled. [15:25](https://youtu.be/Ao2HUjjhlmQ?t=925) - Counterpoint: sometimes the heat sinking is exactly what you want — e.g. a QFN exposed pad tied into all the surrounding GND copper is a useful heat sink, though it brings assembly challenges. [15:50](https://youtu.be/Ao2HUjjhlmQ?t=950) - Vias: no thermal reliefs — "as a complete default"; he doesn't think he's ever used thermal reliefs on vias. He'd always leave via connections as direct connect unless there's a very, very good reason. [17:13](https://youtu.be/Ao2HUjjhlmQ?t=1033) [18:05](https://youtu.be/Ao2HUjjhlmQ?t=1085) ## Spoke sizing - Spoke size depends on pad size, current and power into/out of the part, and inductance requirements; there's an IPC guideline. [16:10](https://youtu.be/Ao2HUjjhlmQ?t=970) - Rule of thumb for a square pad: take 60 % of the pad side, divide by the number of spokes. [16:30](https://youtu.be/Ao2HUjjhlmQ?t=990) | Pad side | 60 % | 2 spokes | 4 spokes | Video | |---|---|---|---|---| | 1 mm | 0.6 mm | 0.3 mm each | 0.15 mm each | [16:40](https://youtu.be/Ao2HUjjhlmQ?t=1000) | - Details in IPC-2221 and IPC-2222. [16:55](https://youtu.be/Ao2HUjjhlmQ?t=1015) - His generic default when there are no particular requirements, for ~0603-size parts: about 0.3 or 0.25 for SMD pads, similar for TH pads — a good starting point, including for hand soldering. [17:52](https://youtu.be/Ao2HUjjhlmQ?t=1072) ==Caption garbled ("3.3 or 0.25.25 25"); unclear which value is air gap vs conductor width — check the rule dialog on screen.== For comparison, in #166 he used a 0.3/0.3 gap/spoke in KiCad — see [[KiCad 9 MCU Board Design Workflow]]. ## Setting it up (Altium) - Design Rules → Polygon Connect: *Simple* applies one style to everything (relief or direct); he uses *Advanced* to set relief properties per connection type — TH pad, SMD pad, via. [17:25](https://youtu.be/Ao2HUjjhlmQ?t=1045) - Per type you set the air gap width, conductor width and number of conductors. [17:46](https://youtu.be/Ao2HUjjhlmQ?t=1066) - Per-pad override: select the pad → Properties → Relief. You can also write custom rules that pick out pads of certain dimensions and give them their own relief. [18:19](https://youtu.be/Ao2HUjjhlmQ?t=1099) # Stitching Vias - The grounded vias scattered around the board are stitching vias — very important, especially with several same-net pours around the board. [18:45](https://youtu.be/Ao2HUjjhlmQ?t=1125) - Placed at intervals wherever there's a pour, tying all the GND fills together vertically (Z axis). [19:00](https://youtu.be/Ao2HUjjhlmQ?t=1140) - Two jobs: - Every top/bottom GND pad gets a low-impedance, low-inductance via to the internal GND planes. [19:25](https://youtu.be/Ao2HUjjhlmQ?t=1165) - The rest (not next to pads) tie the pours together to keep impedance low across a wide bandwidth, into RF and high frequencies. [19:58](https://youtu.be/Ao2HUjjhlmQ?t=1198) - He also runs them around the perimeter (covered in his via fencing / edge plating video). [20:10](https://youtu.be/Ao2HUjjhlmQ?t=1210) - Without stitching, a pour region fed from only one side is essentially floating at RF on the other, and can resonate and act as an antenna. [20:31](https://youtu.be/Ao2HUjjhlmQ?t=1231) - The larger an unstitched pour, the lower its resonant frequency — these become small patch antennas. [21:04](https://youtu.be/Ao2HUjjhlmQ?t=1264) ## Spacing rule of thumb 1. Find the maximum frequency of interest. Analog: straightforward, v = λf. Digital: relate rise/fall times to an approximate knee frequency (an effective analog bandwidth). [21:04](https://youtu.be/Ao2HUjjhlmQ?t=1264) [21:15](https://youtu.be/Ao2HUjjhlmQ?t=1275) 2. Calculate the wavelength, accounting for the slower propagation in the dielectric. [21:36](https://youtu.be/Ao2HUjjhlmQ?t=1296) 3. Divide by a constant: 8, or 20 for a very strict approach (λ/20). Apply across the board wherever there are pours. [21:36](https://youtu.be/Ao2HUjjhlmQ?t=1296) - Compare #166: λ/10–λ/20 — see [[KiCad 9 MCU Board Design Workflow]]. ## Workflow and cleanup - He typically adds stitching at the end of the layout but plans room for it during the design — you don't want to be left with lots of unstitched pour areas. [22:00](https://youtu.be/Ao2HUjjhlmQ?t=1320) - Areas you can't stitch properly (and that aren't doing much): add a polygon pour cutout. In Altium: `P` → Polygon Pour Cutout, draw the region; cutouts can be multi-layer or per-layer. [22:10](https://youtu.be/Ao2HUjjhlmQ?t=1330) [22:22](https://youtu.be/Ao2HUjjhlmQ?t=1342) - He also does this cutout-based cleanup at the end. [22:44](https://youtu.be/Ao2HUjjhlmQ?t=1364) - Other options for unstitched areas: the pour's *Remove Islands* setting; and he suggests always ticking *Remove Dead Copper*. [25:10](https://youtu.be/Ao2HUjjhlmQ?t=1510) # Outer Layers and Copper Balance - Is pouring the top and bottom layers actually beneficial? It can make things worse on signal and power layers when uncontrolled — no proper stitching, no cleanup, pours creeping close to controlled-impedance traces. [22:50](https://youtu.be/Ao2HUjjhlmQ?t=1370) - So a common guideline is to not pour copper on outer/signal layers at all. [23:10](https://youtu.be/Ao2HUjjhlmQ?t=1390) - The counter-argument is copper balance: uneven copper distribution (between layers, or across the XY plane) is a manufacturing risk because copper and the fiberglass dielectric have different coefficients of thermal expansion, during pressing and during assembly. [23:16](https://youtu.be/Ao2HUjjhlmQ?t=1396) - Keeping copper balanced in all axes mitigates warping and bending; imbalance can increase bow and twist → reliability issues like cracked copper, plus assembly problems if you need a flat board. [23:49](https://youtu.be/Ao2HUjjhlmQ?t=1429) [24:21](https://youtu.be/Ao2HUjjhlmQ?t=1461) - If you don't want to pour/balance, talk to your manufacturer about whether the board is manufacturable without it — manufacturers often add copper thieving themselves, but discuss it with them. [24:21](https://youtu.be/Ao2HUjjhlmQ?t=1461) - He strongly recommends Rick Hartley's *Secrets of PCB Optimisation* for more on why copper balancing is needed. [24:40](https://youtu.be/Ao2HUjjhlmQ?t=1480) - **His approach**: these days he typically pours copper on all layers — at the cost of a lot of time spent cleaning up pours, checking stitching, and keeping pours away from sensitive circuitry like controlled-impedance traces. It's his personal approach, varies board to board: "There is no generic blanket statement for this." [24:45](https://youtu.be/Ao2HUjjhlmQ?t=1485) # Hatched vs Solid Fills - For rigid PCBs, solid fills. [25:20](https://youtu.be/Ao2HUjjhlmQ?t=1520) - Hatched fill is available in pretty much any ECAD tool, with different methods — horizontal, vertical, 45°, 90°. [25:28](https://youtu.be/Ao2HUjjhlmQ?t=1528) - In his opinion hatching is predominantly for flexible PCBs: a hatched plane along the bend line reduces the risk of cracking and makes the board easier to bend. [25:45](https://youtu.be/Ao2HUjjhlmQ?t=1545) - Rigid: "pretty much always" solid. Flex / rigid-flex: typically hatched, to avoid cracking during bending and improve mechanical flexibility. [26:03](https://youtu.be/Ao2HUjjhlmQ?t=1563) # Altium Quick Reference | Task | Where | Video | |---|---|---| | Copper clearances | Design Rules → Clearance → copper row | [5:10](https://youtu.be/Ao2HUjjhlmQ?t=310) | | Neck removal | Pour properties → *Remove Necks Less Than* (+ *Obey rules* checkbox) | [8:19](https://youtu.be/Ao2HUjjhlmQ?t=499) | | Island removal | Pour properties → *Remove Islands Less Than* | [9:26](https://youtu.be/Ao2HUjjhlmQ?t=566) | | Dead copper | Pour properties → *Remove Dead Copper* | [25:10](https://youtu.be/Ao2HUjjhlmQ?t=1510) | | Pour order | Tools → Polygon Pours → Polygon Manager | [11:15](https://youtu.be/Ao2HUjjhlmQ?t=675) | | Relief/direct per connection type | Design Rules → Polygon Connect → Advanced | [17:25](https://youtu.be/Ao2HUjjhlmQ?t=1045) | | Per-pad relief | Pad Properties → Relief | [18:19](https://youtu.be/Ao2HUjjhlmQ?t=1099) | | Cutout | `P` → Polygon Pour Cutout | [22:22](https://youtu.be/Ao2HUjjhlmQ?t=1342) | | Solid/hatched | Pour properties → select *Hatched* (default solid) | [25:28](https://youtu.be/Ao2HUjjhlmQ?t=1528) | # KiCad Equivalents Not from this video — a mapping to KiCad terms, using [[KiCad 9 MCU Board Design Workflow]] (Phil's Lab #166) where it covers the same setting. | Altium (this video) | KiCad | Note | |---|---|---| | Polygon pour | Zone | | | Polygon Manager pour order | Zone Properties → Priority level | ==verify which way round priority fills== | | Remove Necks Less Than | Zone Properties → Minimum width | #166: 0.15–0.2 | | Remove Islands / Dead Copper | Zone Properties → Remove islands | #166: remove islands | | Polygon Connect (relief) | Zone Properties → Pad connections, thermal relief gap / spoke width | #166: 0.3 / 0.3 | | Per-pad relief | Pad `E` → Connections → Solid | From #166 | | Via connection | Vias connect solid to zones | ==verify== — matches his default either way | | Polygon Pour Cutout | Rule Area with "keep out zone fills" | From #166 | | Hatched fill | Zone Properties → Fill: hatch pattern | | | Repour all | `B` (refill all zones) | From #166 | # References - [[Phil's Lab 176 Transcript]] — raw timestamped transcript this note was distilled from - [[KiCad 9 MCU Board Design Workflow]] — Phil's Lab #165/166: ground-zone settings, thermal reliefs and stitching applied hands-on in KiCad - [[PCB Layout Rules to Never Break]] — Predictable Designs; overlapping rules on stitching vias and pours for high current - [[JLCPCB Design Notes]] — JLC capabilities page is where the fab minimums come from - [[KiCad Design Tips]] - [[PCB Design Common Mistakes]] — Phil's Lab #18 (2021): earlier take on fab minimums, solid GND planes vs split power planes, decoupling vias # Changelog ## 2026-09-24 - Note created from Phil's Lab #176 (auto-captions via yt-dlp); companion transcript saved as [[Phil's Lab 176 Transcript]]. - Linked [[PCB Design Common Mistakes]] (Phil's Lab #18) under References.