#pcb #layout #stm32 #stm32g0 #lqfp #six-layer #electronics #hardware-design # Overview Layout playbook for an **STM32G0B1CBT6** in **LQFP-48, 7×7 mm body, 0.5 mm pitch** on a **6-layer** board with USB, an HSE crystal, and ADC inputs. Written for a first fine-pitch board. The headline: **LQFP-48 at 0.5 mm pitch is not a hard package.** All 48 pins are on the perimeter — 12 per side — so every pin has a straight path to open board. There is no exposed thermal pad on this package, so no via-in-pad, no microvias, no HDI. On 6 layers you have far more routing resource than a 48-pin MCU needs. The difficulty on this board is *not* escaping the chip; it's the three things beginners get wrong around it: **where the decoupling caps sit, what the return current does when a signal changes layers, and whether the pinout was chosen before or after placement.** Related: [[PCB Layout Rules to Never Break]] · [[KiCad 9 MCU Board Design Workflow]] · [[KiCad Design Tips]] · [[JLCPCB Design Notes]] # Resources ## Watch these first | Video | Why | |---|---| | [KiCad 6 STM32 PCB Design Full Tutorial — Phil's Lab #65](https://www.youtube.com/watch?v=aVUqaB0IMh4) | End-to-end STM32 board in KiCad: schematic → LQFP fanout → decoupling → USB → fab. Closest thing to your exact project. | | [PCB Stack-Up and Build-Up — Phil's Lab #56](https://www.youtube.com/watch?v=QAOEtfvCaMw) | Core/prepreg build-up and how to choose layer ordering. Answers "what should my 6 layers be?" | | [Mini 6-Layer Mixed-Signal Hardware Design Walkthrough — Phil's Lab #78](https://www.youtube.com/watch?v=AxEL3eESL9I) | A real 6-layer board at your exact layer count, with the layer-by-layer reasoning spoken out loud. | | [Tutorial #4: How To Do PCB Layout (Step by Step) — Robert Feranec](https://www.youtube.com/watch?v=8TUHE6TFy1A) | Chapters at 23:33 "Connecting LDO, MCU fanout" and 28:03 "Fanout pull-ups, button, accelerometer". The most literal "how do I route a microcontroller" video there is. | | [How to Achieve Proper Grounding — Rick Hartley](https://www.youtube.com/watch?v=ySuUZEjARPY) | 2 hours, worth all of them. Why you never split ground, and why return current — not trace width — decides whether your board works. | ## Then these - [PCB Vias 101 — Phil's Lab #77](https://www.youtube.com/watch?v=WPT96w3eLAM) — via geometry, tenting, stitching, via-in-pad. Watch before committing to a fanout via size. - [QFN PCB Design Tips & Tricks — Phil's Lab #144](https://www.youtube.com/watch?v=hOamoJ15hmA) — nearest fine-pitch-package-specific video: pad geometry, paste stencil, thermal vias. - [PCB Design for EMI & SI — Phil's Lab #64](https://www.youtube.com/watch?v=VtzPL8wQ8-E) — rise times, critical length, reference planes, layer transitions. The "why" under the stackup rules. - [PDN Basics & Measurements — Phil's Lab #161](https://www.youtube.com/watch?v=-DdkEBtA5vk) — target impedance and where decoupling actually helps, measured. - [Differential Pairs — Phil's Lab #83](https://www.youtube.com/watch?v=xwrdvhm4vgw) — for USB D+/D−. - [Layer Ordering, Pouring and Stackup, with Rick Hartley — Robert Feranec](https://www.youtube.com/watch?v=52fxuRGifLU) — walks 2/4/6/8/10-layer orderings explicitly. Short cut: [highlights](https://www.youtube.com/watch?v=60RxCiZuD9E). - [Return Current Path, with Eric Bogatin](https://www.youtube.com/watch?v=icRzEZF3eZo) — short; makes plane-split and layer-hop mistakes obvious forever. - [EEVblog #1029 — BGA PCB Fanout](https://www.youtube.com/watch?v=_1dr5FWYDgE) — BGA-framed, but the via/mask/annular-ring DFM numbers apply to 0.5 mm QFP escape. ## Written - **[AN5096 — Getting started with STM32G0 Series hardware development](https://www.st.com/resource/en/application_note/an5096-getting-started-with-stm32g0-series-hardware-development-stmicroelectronics.pdf)** — ST's own reference schematic, decoupling values, and layout rules. Read §5 (§5.1 layers, §5.2 partitioning, §5.3 grounding, §5.4 decoupling). This is the primary source for this board. - **[DS13560 — STM32G0B1xB/xC/xE datasheet](https://www.st.com/resource/en/datasheet/stm32g0b1cc.pdf)** — Figure 5 (LQFP48 pinout), Table 12 (pin definitions), Figure 44 (recommended footprint). - **[AN4879 — USB hardware and PCB guidelines using STM32 MCUs](https://www.st.com/resource/en/application_note/an4879-introduction-to-usb-hardware-and-pcb-guidelines-using-stm32-mcus-stmicroelectronics.pdf)** — the USB section below is drawn from this. - [6-Layer PCB Stackup Design Guidelines](https://resources.altium.com/p/6-layer-pcb-design-guidelines-pcb-design) and [Designing a 6-Layer PCB Stackup for Enhanced EMC](https://resources.altium.com/p/designing-6-layer-stackup-enhanced-emc) — Zach Peterson, Altium. - [Decoupling Capacitor Connections: Traces or Vias?](https://resources.altium.com/p/decoupling-capacitor-connections-traces-or-vias) — settles "cap beside the pin vs. on the back side under it" with loop-inductance reasoning. - [How to do BGA fanout — VIAs & Layers](https://fedevel.com/blog/how-to-do-bga-fanout-vias-layers) — Feranec. His one-via-per-power-pad rule transfers straight to LQFP. - [PCB Layout & Decoupling — why it's so complicated](https://fedevel.com/blog/pcb-layout-decoupling-explained-why-it-is-so-complicated-part-1) — Feranec, measuring decoupling on real boards. - [Successful PCB Grounding with Mixed-Signal Chips](https://www.analog.com/en/resources/technical-articles/successful-pcb-grounding-with-mixedsignal-chips--follow-the-path-of-least-impedance.html) — Analog Devices. Why not to split AGND/DGND. - [Bogatin's Rules of Thumb](https://www.colorado.edu/faculty/bogatin/publications/rules-thumb) — free reference sheet (33 EDN rules): bandwidth from rise time, loop inductance, when a trace becomes a transmission line. - [Decoupling & Vcc pin configuration for STM32 MCUs](https://community.st.com/stm32-mcus-products-25/decoupling-vcc-pin-configuration-for-stm32-mcus-136117) — forum thread, not ST guidance, and it's a G0B0 in LQFP-64 rather than your part. Still useful: a beginner posts their VBAT/VREF+/VDD tie-together and via layout, and an ST moderator approves it with a caveat about VREF+ tied to VDD during ADC sampling. # Design ## Step 0 — Choose the pinout after placement, not before This is the single biggest lever and it happens in CubeMX, not in the PCB editor. Almost every G0 peripheral is remappable across several pins. So: 1. Sketch the board outline and drop the **connectors and mechanical parts** in their real positions first — USB connector, SWD header, whatever the ADC inputs come from. 2. Place the MCU and **rotate it** so that each functional group faces the edge it has to reach. 3. *Then* open CubeMX and assign peripherals so signals that need to go east land on the east side of the package. Getting this right eliminates most of the routing pain before you draw a single track. Getting it wrong is how a 48-pin board ends up with traces looping all the way around the chip. Constraints you can't move: **PA13/PA14 (SWD)**, **PA11/PA12 (USB)**, **PF0/PF1 (HSE)**, **PC14/PC15 (LSE)**, **PF2 (NRST)**, and the power pins. Everything else is negotiable. Orient the chip so those fixed groups point at the right places, and let the flexible signals absorb the rest. ## Package and footprint | Item | Value | |---|---| | Body | 7.0 × 7.0 mm (D1/E1 nom) | | Lead tip span | 9.0 mm nom (D/E), 8.8–9.2 mm | | Pitch | 0.50 mm | | Lead width `b` | 0.17 / 0.22 / 0.27 mm | | Height | 1.60 mm max | | Thermal pad | **None** | | Generic land pattern | pad **0.30 mm wide × ~1.2–1.6 mm long**; inner land span ~6.6 mm, outer ~9.8 mm | | IPC-7351 designator | `QFP50P900X900X160-48N` | The KiCad footprint `LQFP-48_7x7mm_P0.5mm` matches this and is fine to use as-is. - ==Confirm ST's own recommended pad length in DS13560 Rev 6, Figure 44 (p. 136) before you finalise the footprint — sources disagree between 1.2 mm and 1.6 mm pad length. Longer toe fillet is easier to inspect and hand-rework; shorter gives more escape room.== - Pitch 0.50 − pad width 0.30 = **0.20 mm of copper gap between adjacent pads.** That is the number that governs everything below. - No thermal pad means **no via-in-pad anywhere on this part**, and no paste-stencil window design to worry about. Assembly is ordinary reflow. This package is well inside JLCPCB/PCBWay standard assembly. ## Stackup Use this arrangement: | Layer | Assignment | Notes | |---|---|---| | **L1** | Signal (top) | Components, fanout, short escapes, USB pair | | **L2** | **GND — solid, unbroken** | Reference for L1 *and* L3 | | **L3** | Signal | Main routing layer | | **L4** | Power (3V3 pour) + spare signal | Tightly coupled to L5 GND | | **L5** | **GND — solid, unbroken** | Reference for L4 and L6 | | **L6** | Signal (bottom) | Decoupling caps, escapes, slow signals | Why this one, in order of importance: - **Every signal layer has a ground plane immediately adjacent.** L1→L2, L3→L2, L6→L5. That is the whole point of paying for 6 layers. - **L1 and L3 share the same reference plane (L2).** So an L1→L3 layer change keeps the return current on the same copper — the return just hops to the other face of L2 through the via barrel. That transition is nearly free and needs no stitching via. This is a big deal: it means most of your routing can move between L1 and L3 without thinking hard. - **L4 (PWR) is tightly coupled to L5 (GND)**, forming plane capacitance that helps at frequencies above where your discrete caps stop working. - L2 and L5 are **never** cut, split, or routed through. If you find yourself wanting to run "just one trace" on L2, you have made a mistake somewhere else. Two practical notes: - Look up your fab's actual 6-layer build-up. Layer pairs are **not** evenly spaced — outer pairs (L1–L2, L5–L6) are usually thin prepreg (~0.1 mm) and the middle is thick core. The thin L1–L2 gap is exactly what makes your top-side decoupling vias short and low-inductance, so this asymmetry works in your favour. - Rick Hartley's variant is `SIG / GND / SIG / SIG / GND / SIG` with power routed as fat traces and local pours rather than a dedicated plane. That's arguably better for a board with several rails. On a single-3V3 MCU board, the plane on L4 is simpler and fine. ## Fanout Escape strategy for a 48-pin QFP is different from BGA advice you'll find online — you have perimeter pins and 12 per side, so this is mostly a placement problem. **Rules:** 1. **Do not route between adjacent pads under the body.** You have 0.20 mm of gap. Squeezing a 0.09 mm trace through leaves ~0.055 mm clearance either side — technically inside JLCPCB's 4+ layer capability, but there is no reason to do it on this board. Escape radially instead. 2. **Power and ground pins get a via each, immediately, before anything else.** Drop the via right off the end of the pad — a short 0.3–0.5 mm stub of copper, then via down to L2 (GND) or L4 (PWR). One via per pin, not one shared via for two pins. 3. **Signals that only travel a short distance stay on L1.** With 12 pins per side you can usually escape 6–8 per side on the top layer alone. 4. **Everything else drops to L3.** Place those vias in **two staggered rows** outside the pad tips — row 1 at roughly 0.6 mm from the pad end, row 2 at ~1.1 mm. Staggering gives each row an effective 1.0 mm pitch, which is comfortable. 5. **Do not punch a wall of vias through the region directly under the chip.** Every signal via is a hole in L2. A tight ring of 40 vias turns your ground plane into swiss cheese right where the return currents are densest. Escape outward on L1 first, transition to L3 *outside* the package outline. **Via sizing for fanout** (JLCPCB 6-layer): | Use | Drill / Pad | |---|---| | Fanout, tight areas | 0.20 / 0.45 mm | | General signal + stitching | 0.30 / 0.50 mm | | Power / decoupling | 0.30 / 0.60 mm, or two 0.30 vias in parallel | - ==Confirm current JLCPCB 6-layer minimums at order time — reported as 0.0889 mm (3.5 mil) trace/space and 0.20 mm min drill for multilayer, with via-in-pad free on 6–20 layer stackups, but these change.== - Suggested starting DRC: **0.15 mm trace / 0.15 mm clearance** general, dropping to **0.10 mm** only inside the fanout region. Wide default rules keep the rest of the board manufacturable and cheap. ## Decoupling — the part that actually matters ST's requirement (AN5096 §5.4 and Fig. 1): | Net | Caps | |---|---| | Each VDD/VSS pair | **100 nF** ceramic | | Bulk, once per device | **4.7 µF** | | VREF+ | **100 nF + 1 µF** (raise the 1 µF up to 10 µF if you sample slowly and draw peaks) | | NRST | **100 nF** | - ==Count the VDD/VSS pairs on your symbol and put one 100 nF on each. Don't assume a number — check DS13560 Table 12.== - Use **0402 X7R/X5R, 16 V or 25 V**. 0402 has meaningfully lower parasitic inductance than 0603, and on a 0.5 mm-pitch board you want the small body anyway. Don't use Y5V. **The technique — this is where beginners lose it.** The capacitor does nothing by itself; what matters is the *loop*: plane → via → pad → cap → pad → via → plane. Loop inductance kills high-frequency performance. So: - **Good:** cap sits on the **bottom side (L6) directly under the VDD/VSS pin pair**, each terminal with its own via straight up. Or on the **top side immediately beside** the pin pair, each terminal with its own via straight down. ST explicitly endorses both — "as close as possible to, or below, the appropriate pins on the underside of the PCB." - **Bad:** cap placed a few mm away with a trace running to a shared via. That trace is inductance in series with your capacitor and undoes most of the benefit. - **Worse:** one via serving two cap terminals, or a cap whose ground goes through a long thin neck into the pour. - With L2 GND right beneath L1, a top-side cap's ground via is only ~0.1 mm of barrel. That is about as low-inductance as you can get without buried caps. Put the 4.7 µF bulk near the chip but it doesn't need to be surgical — it's handling low-frequency droop, not nanosecond edges. The 100 nFs are the ones that must be tight. ## Power supply pins STM32G0 pin naming is unusual and worth reading carefully before you copy an F4/H7 reference design: - ST names the G0 supply pins **VDD/VDDA** and **VSS/VSSA**. On the small G0 packages these are genuinely combined and you cannot isolate the analog supply at all. - ==On LQFP-48 specifically, an ST community answer states the 48-pin package is the smallest G0 that gives you independent analog supply capability — implying a separate VDDA. Verify against DS13560 Table 12 before you design in a ferrite bead.== - **VBAT** is a separate pin. If you're not fitting a backup battery, **tie VBAT to VDD** (AN5096's explicit recommendation). Don't leave it floating. - **VREF+** is a separate pin on LQFP-48 and gets its own 100 nF + 1 µF. If VDDA ≥ 2 V, VREF+ must sit between 2 V and VDDA. Tie it to VDDA if you're not using an external reference. Ground it only if you use neither ADC nor DAC. - There is **no VCAP/VCORE pin** on G0 — the core regulator is fully internal. No external core capacitor. If you're cribbing from an F1/F4 schematic, delete that part. - There is **no VDDUSB rail** on G0. The USB transceiver runs from VDD, which is another reason the VDD decoupling has to be tight. **If VDDA is separate:** ferrite bead in series from VDD to VDDA (something like 600 Ω @ 100 MHz, low DCR, rated well above your actual current), plus 1 µF + 10 nF from VDDA to ground on the chip side of the bead. Only worth it if you have a switching regulator on the board. If you're on an LDO from USB 5 V, the bead buys you very little and can ring — a plain 0 Ω or a direct connection is defensible. **If VDDA is combined:** you have no supply isolation lever. Your ADC quality then comes entirely from VREF+ filtering, input RC filters, and physical placement — see the analog section. ## HSE crystal (PF0 / PF1) - Place the crystal and both load caps **as close as physically possible** to PF0/PF1 — ideally the crystal body within a few mm, load caps touching it. AN5096 is explicit: distance costs you startup margin and adds distortion. - **Star the load-cap grounds.** Both caps' ground pads meet at one small copper island, and that island gets one (or two adjacent) short vias to L2. Don't route each cap ground separately off into the pour — that creates a loop across the oscillator. - **Local ground pour** on L1 surrounding the crystal, stitched to L2 with several vias. Some designers add a guard ring; on a 6-layer board with solid L2 underneath, a well-stitched local pour does the same job. - **Keep-out.** Nothing routed under the crystal on L1 *or* L3. Keep L2 solid beneath it. No switching regulator, no USB, no fast digital within ~10 mm if you can manage it. - **Load cap value:** `C = 2 × (CL − C_stray)`, where `C_stray` is pin + trace capacitance, typically 3–5 pF. For a crystal specced at CL = 8 pF and C_stray = 4 pF, use 8 pF caps. Use C0G/NP0, never X7R. - Worth knowing: the G0B1's USB is **crystal-less capable** — HSI48 trimmed by the CRS off the USB SOF packet. So for a USB *device* you don't strictly need the crystal at all. Keep it if you want accurate timing elsewhere (or if you'll ever be a USB host, where HSI48 isn't accurate enough); drop it if you want the board simpler. ## USB (PA11 / PA12) From AN4879. Several things you do **not** need, which is where most beginner USB schematics go wrong: - **No series resistors on D+/D−.** The 40.5–49.5 Ω matching impedance is built into the STM32 pad driver. - **No external 1.5 kΩ pull-up on D+.** It's embedded. - **No VDDUSB decoupling** — there's no such pin on G0. What you do need: - **ESD protection right at the connector**, before the traces head toward the MCU. ST recommends **USBLC6-2SC6** on D+/D−, plus something like **ESDA7P60-1U1M** on VBUS. Put it physically between the connector and everything else — protection placed after a long trace protects nothing. - **Route D+/D− as a coupled differential pair** on L1, referenced to L2 GND, from connector to MCU with no layer changes. Nominal target is 90 Ω differential. - Honest framing: this is **USB Full Speed at 12 Mbps** on a small board. Exact impedance is close to irrelevant at that edge rate. What actually matters is that the two traces stay *together*, stay over *unbroken* ground, and are roughly equal length. Don't burn a day on impedance calculations; do refuse to let them separate or cross a plane gap. - **VBUS sensing** — mandatory for a self-powered design, optional if bus-powered. Divider **33 kΩ / 82 kΩ** into a 5 V-tolerant pin keeps the node under 4 V for a 3.0–3.6 V VDD. Route VBUS well away from D+/D−. - **VDD ≥ 3.0 V** for USB 2.0 FS compliance. The transceiver works down to 2.7 V but the eye diagram fails below 3.0 V. - Connector shield: tie to GND. A direct connection is normal on a small board; the 1 MΩ ∥ 4.7 nF arrangement is the alternative if you're worried about shield currents. ## Analog and ADC The general principle, and it's the opposite of what a lot of older material says: **do not split the ground plane.** One solid, uninterrupted GND. Splitting it forces return currents to detour around the gap, which makes noise worse, not better. Control analog noise by *placement and partitioning*, not by cutting copper. What actually helps: - **VREF+ filtering** — 100 nF + 1 µF minimum, up to 10 µF if you sample at low rates with current peaks. This is your highest-leverage move. - **RC filter on each analog input** — a series R (100 Ω – 1 kΩ) plus a cap to ground at the pin. Size the cap so the source can recharge the ADC sampling capacitor within your sample time; 100 pF – 1 nF is a common starting point. Keep the cap's ground via right at the pin. - **Route analog traces on L1 over solid L2 ground**, short, and don't let them change layers. If they must, put a GND stitching via right alongside. - **Physical separation.** Put analog inputs, the ADC-adjacent pins, and their filters on one side of the chip. Put the switching regulator, USB, and any fast digital on the other side of the board. This is what "partitioning" means in AN5096 §5.2 — a placement decision, not a copper decision. - Don't run digital signals under or beside analog traces on adjacent layers. ## SWD and BOOT0 — read this before you place the header - **SWDIO = PA13, SWCLK = PA14.** Both have internal pull-up/pull-down. **No external resistors needed.** - **PA14 is also BOOT0.** This trips people up. Anything you hang on PA14 — a BOOT0 button, a pull-down resistor — is sitting on your SWD clock line. If you fit one, keep it **≥ 10 kΩ** and physically short, or it will fight the debugger. - On G0 the boot source is selected by **option bytes** by default; the BOOT0 pin only takes effect once `nBOOT_SEL` is programmed. So you may not need a BOOT0 circuit at all. Consider a pad or a solder jumper rather than a permanent button. - **NRST is PF2-NRST**, with a 100 nF to ground. Nothing else — no series resistor, no pull-up (there's an internal one). Cap close to the pin with its own via. - Bring out **SWDIO, SWCLK, GND, VDD** (for target-voltage detect) and **NRST**. A 5-pin 1.27 mm header or a Tag-Connect footprint both work. Put it at a board edge you can reach with the board mounted. - Keep SWD traces short and over ground. They're not fast, but a marginal SWCLK is a miserable thing to debug. ## Ground pour and stitching - Flood **L1 and L6 with GND** and stitch generously. A poorly-stitched pour is worse than no pour — isolated copper islands act as antennas. Either stitch it properly or don't pour. - **Stitching vias every ~5 mm** across the pours and around the board perimeter, bonding L2 and L5 together. - Ring the board edge with stitching vias inset a few mm from the outline. - Keep the pour under the MCU intact — don't let KiCad's fill carve it into slivers between fanout vias. Check the filled zones visually at the end; slivers and orphaned islands are easy to miss. # Decisions | Decision | Choice | Why | |---|---|---| | Layer count | 6 | Gives L1 and L3 a shared solid reference (L2), plus a power plane. Overkill for pin count, correct for peace of mind. | | Stackup | `SIG / GND / SIG / PWR / GND / SIG` | Every signal layer adjacent to ground; L1↔L3 transitions keep the same reference. | | Fanout | Dog-bone vias, staggered two rows, outside the package outline | No thermal pad → no via-in-pad needed. Keeps L2 intact under the chip. | | Decoupling | 0402 100 nF per VDD/VSS pair + 4.7 µF bulk | AN5096 §5.4. 0402 for lower ESL. | | Cap placement | Top side beside the pins, or bottom side directly under | Shortest loop. Never a trace-to-shared-via. | | Ground | One solid plane, no splits | Rick Hartley / ADI. Splits make return paths worse. | | USB series resistors | None | Impedance is embedded in the STM32 pad (AN4879 §3.1). | | Crystal | Optional | G0B1 USB is crystal-less capable via HSI48 + CRS. Fit it only if you need accurate timing elsewhere. | # TODO - ==Verify LQFP-48 pin numbers against DS13560 Rev 6, Figure 5 (p. 38) and Table 12 (~p. 45) — including how many VDD/VSS pairs there are.== - ==Confirm whether VDDA is a separate pin on this package before designing in a ferrite bead.== - ==Check ST's recommended footprint pad dimensions in DS13560 Figure 44 (p. 136) — 1.2 mm vs 1.6 mm pad length is unresolved.== - ==Pull the actual 6-layer build-up (dielectric thicknesses) from the fab and record which layer pairs are tightly coupled.== - ==Decide crystal vs. crystal-less before finalising the pinout — it frees PF0/PF1 if dropped.== - ==Confirm JLCPCB current 6-layer minimums (trace/space, min drill, via-in-pad pricing) at order time.== # Pre-order checklist Run this before generating gerbers, in addition to [[PCB Layout Rules to Never Break]]: - [ ] Every VDD/VSS pair has its own 100 nF, with **its own via per terminal**, no shared vias, no traces to vias - [ ] 4.7 µF bulk present; VREF+ has 100 nF + 1 µF; NRST has 100 nF; VBAT tied to VDD - [ ] L2 and L5 are completely unbroken — no traces, no splits, no via cluster tunnelling through under the MCU - [ ] Every signal that changes reference planes has a GND stitching via within ~2 mm - [ ] USB D+/D− stay paired, on L1, over solid ground, no layer changes; ESD part is at the connector - [ ] Crystal load caps star-grounded to a single via pair; nothing routed under the crystal on any layer - [ ] PA14 has nothing low-impedance on it (BOOT0/SWCLK conflict) - [ ] Analog inputs filtered at the pin, routed over ground, away from the regulator and USB - [ ] Pours stitched every ~5 mm; board edge ringed; no orphaned copper islands after fill - [ ] DRC clean against the fab's *actual* published rules, not KiCad's defaults - [ ] 3D view checked for footprint/courtyard collisions at 0.5 mm pitch # References - [[PCB Layout Rules to Never Break]] — John Teel's 11 rules; the plane-split and decoupling rules overlap directly with this note - [[KiCad 9 MCU Board Design Workflow]] — Phil's Lab MSPM0 walkthrough; same process applied hands-on in KiCad 9 - [[KiCad Design Tips]] — plugins, themes, board-setup habits - [[JLCPCB Design Notes]] — fab-specific gerber export, via covering, process edges - [ST AN5096](https://www.st.com/resource/en/application_note/an5096-getting-started-with-stm32g0-series-hardware-development-stmicroelectronics.pdf) · [ST AN4879 (USB)](https://www.st.com/resource/en/application_note/an4879-introduction-to-usb-hardware-and-pcb-guidelines-using-stm32-mcus-stmicroelectronics.pdf) · [DS13560 (STM32G0B1)](https://www.st.com/resource/en/datasheet/stm32g0b1cc.pdf) - [Phil's Lab video index](https://www.phils-lab.net/videos) — canonical list, episode numbers and links