RP2354A Hardware Design Reference

#rp2354 #rp2350 #raspberry-pi #mcu #pcb #hardware-design #klipper #electronics #power-supply # Overview Design reference for the **RP2354A** — the QFN-60 RP2350 variant with 2 MB of flash stacked in package. Extracted 2026-09-18 from the RP2350 datasheet (build 2025-07-29, RP-008373-DS-2) and *Hardware design with RP2350* (rebuilt 2026-08-24, Release 3 / rev C.1, diagrams updated to the R4-S1 minimal boards). The headline: **RP2354A is an RP2350A with the flash chip already soldered on — same die, same pinout, same package, +$0.20.** What that buys you is one fewer component, one fewer decoupling cap, and no flash sourcing. What it costs you is that **QSPI_IOVDD is locked to 3.3 V** and you inherit a fixed 2 MB. Everything else in this note is really RP2350 design, and applies equally to the flashless part. The thing that will actually cost you time is not the flash — it's the **core switching regulator**, which is prescriptive to the point of naming a single custom Abracon inductor part number, and whose layout Raspberry Pi says must be placed first on the board. Companion to [[Klipper Compatible MCU Comparison]]. Related: [[STM32G0B1CBT6 LQFP-48 Layout Playbook]] · [[JLCPCB Design Notes]] · [[KiCad 9 MCU Board Design Workflow]] · [[PCB Layout Rules to Never Break]] # Resources | Document | Link | |---|---| | **RP2350 datasheet** (errata = Appendix E, stepping matrix = Appendix C) | [PDF](https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf) · stable: [RP-008373-DS](https://pip.raspberrypi.com/documents/RP-008373-DS) | | **Hardware design with RP2350** | [PDF](https://datasheets.raspberrypi.com/rp2350/hardware-design-with-rp2350.pdf) · stable: [RP-008280-DS](https://pip.raspberrypi.com/documents/RP-008280-DS) | | RP2350 product brief (pinouts, package drawings) | [PDF](https://datasheets.raspberrypi.com/rp2350/rp2350-product-brief.pdf) | | **Minimal KiCad reference design — RP2350A** | [RP-010328-CA](https://pip.raspberrypi.com/documents/RP-010328-CA) | | Minimal KiCad reference design — RP2350B | [RP-010329-CA](https://pip.raspberrypi.com/documents/RP-010329-CA) | | A4 stepping PCN (PCN 28) | [PDF](https://pip.raspberrypi.com/categories/1263-pcn/documents/RP-008771-CC/RP235x-A4-stepping-PCN.pdf) | | PCN 32 — Pico 2 products moving to A4 | [PDF](https://pip-assets.raspberrypi.com/categories/1262-pcn/documents/RP-008978-PC/Pico-2-Products-Moving-to-RP2350-A4-Silicon-Stepping) | | All RP2350 documents | [PIP category 1214](https://pip.raspberrypi.com/categories/1214-rp2350) | | Winbond W25Q16JV (the stacked die) | [product page](https://www.winbond.com/hq/product/code-storage-flash-memory/serial-nor-flash/?__locale=en&partNo=W25Q16JV) | | A4 / RP2354 announcement | [raspberrypi.com news](https://www.raspberrypi.com/news/rp2350-a4-rp2354-and-a-new-hacking-challenge/) | There is **no separate errata document** — errata live in datasheet Appendix E as RP2350-E1 … E26. # Design ## 1. What's actually in the package Datasheet §14.3, "Flash in package": - Two stacked die: the **same RP2350 die** as the flashless parts, plus a **Winbond W25Q16JVWI** QSPI NOR flash. 16 Mbit = **2 MB**. - Max QSPI clock of the flash die: **133 MHz**. - "In all other respects, **including pinout**, they are identical to their flashless counterparts." - The flash die's `PADRESETB` is **not connected to anything** — no external pin, no internal RP2350 signal. So there is no hardware reset of the flash. RP2350 initialises it exactly as it would an external flash, with the bootrom's fixed XIP-exit sequence at reset. - ==RP2354A thermal characteristics (Table 1423) are still **TBD** in the current datasheet build. RP2350A QFN-60 is θJA 40.542 °C/W still air, 31.99 @1 m/s, 30.264 @2 m/s, θJB 12.588, θJC 14.315 — use those as a stand-in.== ## 2. QSPI — the pins are still yours The six dedicated QSPI pads (CSn, SCK, SD0–SD3) **connect to both the internal flash die and the external package pins**. You are not locked out. QFN-60 pin numbers and reset states: | Signal | Pin | Reset pull | |---|---|---| | QSPI_SD3 | 55 | up | | QSPI_SCLK | 56 | down | | QSPI_SD0 | 57 | down | | QSPI_SD2 | 58 | up | | QSPI_SD1 | 59 | down | | QSPI_SS | 60 | up | ### Adding a second QSPI device A second flash or **QSPI PSRAM** hangs off the same bus with a secondary chip select from Bank 0 GPIO. Up to 16 MB per chip select. **QMI CS1n is available on GPIO0, GPIO8 and GPIO19** on the QFN-60 (GPIO47 additionally on QFN-80). Datasheet function description: "Auxiliary chip select for QSPI bus, to allow execute-in-place from an additional flash or PSRAM device." On the R4-S1 minimal board, converting U3 from primary to secondary flash is two 0 Ω jumpers: - **Remove R10** (ties QSPI_SS to U3's CS) - **Fit R9** (ties GPIO0 to U3's CS) The RP2350B minimal board's optional second device U4 needs **R11 (0 Ω)**, **R13 (10 kΩ pull-up)** and **C22 (100 nF)**. The pull-up is mandatory, not optional: "the default state of GPIO0 is to be pulled low at power-up, which would cause our flash device to fail." > **Erratum RP2350-E14** — `connect_internal_flash()` always used pin 0 as CS1 and ignored the configured `FLASH_DEVINFO` value. Fixed in the A3 bootrom, so A4 is fine. Only matters if you use CS1 on GPIO8 or GPIO19. Any second flash must meet datasheet §3.3 "Supported flash chips": respond to **03h** serial read with 24-bit addressing at ~1 MHz across all four CPOL/CPHA combinations, plus **02h** page program (256 B), **05h** status read, **06h** write enable, **20h** 4 kB sector erase, and exit any continuous-read/XIP mode on the bootrom's fixed exit sequence. ### QSPI_IOVDD must be 3.3 V This is the one hard constraint RP2354 adds. Table 1441 §14.9.5: | Supply | Min | Typ | Max | |---|---|---|---| | QSPI_IOVDD (**RP2350** only) | 1.62 | 1.8 / 3.3 | 3.63 V | | QSPI_IOVDD (**RP2354** only) | **2.97** | **3.3** | **3.63 V** | Verbatim note under that table: > RP2354 contains an internal 3.3 V flash device, therefore QSPI_IOVDD must be 3.3 V. Furthermore, if the QSPI pins are to be used to connect to an additional flash or PSRAM device, then **IOVDD must be 3.3 V**, as a GPIO is used as QSPI chip select in this case. So on RP2354A you lose the 1.8 V QSPI option outright, and you lose the 1.8 V **IOVDD** option too if you use CS1. ==Minor internal inconsistency: datasheet §14.3 body text says QSPI_IOVDD "must be in the range 2.7 to 3.6 V" while Table 1441 says 2.97–3.63 V. Design to 3.3 V nominal and it doesn't matter.== ### Layout notes specific to RP2354 - "You should account for the **increased high-frequency currents on this [QSPI_IOVDD] supply pin** in your decoupling circuit and PCB layout." - "If you do not require access to the RP2350 QSPI bus from the outside, you should **minimise the track length connected to the QSPI package pins**. This avoids unnecessary emissions and capacitive loading of the QSPI bus." - External flash U3 "can safely be removed from the schematic, or simply left unpopulated" — but **keep the BOOTSEL switch on QSPI_SS**. ## 3. Power ### Rails | Supply | Min | Typ | Max | Notes | |---|---|---|---|---| | VREG_VIN | 2.7 | 3.3 | 5.5 V | core regulator input | | VREG_AVDD | 3.135 | 3.3 | 3.63 V | low-noise; RC-filtered | | DVDD | 1.05 | 1.1 | 1.16 V | transients within ±100 mV | | IOVDD | 1.62 | 1.8 / 3.3 | 3.63 V | below 2.5 V set `VOLTAGE_SELECT=1` | | QSPI_IOVDD (RP2354) | 2.97 | 3.3 | 3.63 V | forced by internal flash | | USB_OTP_VDD | 3.135 | 3.3 | 3.63 V | **must always be provided, even if USB is never used** | | ADC_AVDD | 1.62 | 3.3 | 3.63 V | "performance compromised below 2.97 V"; ADC input must never exceed IOVDD | **Decoupling** (§6.1): 100 nF per power pin generally; the two DVDD pins nearest the regulator get 100 nF each and the DVDD pin furthest from it gets **4.7 µF**; USB_OTP_VDD 100 nF; ADC_AVDD 100 nF; VREG_VIN 4.7 µF. One documented deviation in the RPi minimal design — **QFN-60 pins 53 and 54 share a single cap (C12)** because there's no room, and RPi flags this as a deliberate trade-off that "could have the effect of limiting the maximum speed the design could operate at." **Sequencing** (§6.1.8): with the exception of VREG_VIN and VREG_AVDD, which should come up **together**, the rails may power up or down in any order. Small transients can flow in ADC_AVDD if it comes up before DVDD or goes down after it — harmless, avoidable by bringing DVDD up before or with ADC_AVDD. A single-3.3 V design where DVDD follows shortly after ADC_AVDD is explicitly called acceptable. ### The core regulator 200 mA switching + linear regulator, **fsw 3 MHz**, output settable 0.55–3.30 V, enabled by default, starts in switching mode at 1.1 V nominal. Output is limited to 1.3 V unless `VREG_CTRL.DISABLE_VOLTAGE_LIMIT` is set, and you must set `VREG_CTRL.UNLOCK` before software control — **"the regulator can't be relocked after it's been unlocked."** Three modes: - **Normal** — switching, ≤200 mA. Must be in normal mode before core current exceeds 1 mA. - **Low-power** — linear, ≤1 mA, VOUT ≤1.3 V. "In low-power mode, the output of the regulator is directly connected to DVDD… **Don't put the regulator into low-power mode if DVDD is being powered from an external supply.**" - **High-impedance** — disabled, outputs hi-Z. Only for externally-supplied DVDD; entering it while the on-chip regulator is supplying DVDD **causes a reset event**. Efficiency at 1.1 V out from 3.3 V in: 70 % @10 mA, 72 % @100 mA, 59 % @200 mA. `VOUT_OK` de-asserts at 84/87/90 % of the selected output. ### The inductor — this is the part to get right > LX must be **fully shielded, 3.3 µH ±20%**, max DC resistance **250 mΩ**, saturation current **at least 1.5 A**. **The inductor must be marked for polarity.** — §6.3.8.2 Raspberry Pi worked with **Abracon** to create a custom 2.0×1.6 mm (0806 / 2016 metric) polarity-marked part: **`AOTA-B201610S3R3-101-T`** Why polarity matters, verbatim from §6.3.8.3: > Even with nominally fully shielded inductors, leakage magnetic field coupling into the loop formed by the output VREG_LX node through the inductor and output capacitor (COUT) seems to affect the regulator control loop and output voltage. **Field orientation (and hence inductor orientation) matters** — the inductor has to be the right way around to make sure the regulator operates properly especially at higher output currents and for higher load transients. The practical problem with a generic 0806: winding orientation is impossible to deduce from the outside and is randomly distributed along a reel. The Abracon part has a **polarity dot** and ships on reel all aligned the same way. A wrong-way-round inductor "interferes with the regulator output capacitor (C7), which in turn upsets the control circuitry within RP2350." ==If you substitute: expect degraded regulation, worse transient response and efficiency, and a 50/50 orientation gamble per reel. RPi's own position is that other layouts could tolerate any orientation but "will most likely use a lot more PCB space." Don't substitute on a first spin.== ### Regulator passives | Part | Value | Notes | |---|---|---| | CIN | ≥4.7 µF | max parasitic resistance 50 mΩ | | COUT | 4.7 µF ±20% | max ESR 250 mΩ, max ESL **6 nH**; place between VREG_VIN and VREG_PGND as close to the pins as physically possible | | Second output cap | 4.7 µF | on VOUT/DVDD at **QFN-60 pin 23**, bottom edge — *not* near LX/COUT | | VREG_AVDD filter | **33 Ω + 4.7 µF** | VREG_AVDD draws ~200 µA | | L1 | Abracon AOTA-B201610S3R3-101-T | 3.3 µH, 0806 | Minimal-board BOM: C6/C7/C9 = 4.7 µF 0402, R3 = 33 Ω 0402, L1 = the Abracon part in 0806. ### Regulator layout rules > The most critical part of an RP2350 PCB layout is the core voltage regulator. This should be placed first on any board design and these guidelines **must be strictly followed**. — §6.3.8.1 - VREG_AVDD is noise-sensitive — the 33 Ω/4.7 µF RC is not optional. - CIN needs its **own separate GND via** / low-impedance path back to the RP2350 GND pad. - Keep both switching-phase current loops small, low-impedance and isolated, joined to main GND at **one point**. - **Do not place CIN / LX / COUT on the opposite side of the PCB.** - Minimise parasitics on VREG_LX. - **Cut away copper under the inductor and near the VREG_LX trace.** On ≥4-layer boards also cut copper on layer 2 immediately beneath the LX/VREG_LX node. - Two adjacent GND vias for the high-current return. - CFILT must not share GND vias with CIN/COUT. - **VREG_FB is fed from the output of COUT**, routed so it does not pass directly underneath LX. ### Running DVDD from an external 1.1 V supply Datasheet Fig 21, verbatim: > If the digital core supply (DVDD) is powered from an external 1.1 V supply, the on-chip regulator can be disabled and the application circuit simplified. **Power must still be provided on the regulator's analogue supply (VREG_AVDD) and input supply (VREG_VIN) to power the chip's power-on reset and brown-out detection blocks. But the inductor can be omitted and only a single input capacitor is required. Connect VREG_FB directly to ground.** VREG_LX is left unconnected; VREG_PGND still to GND. The regulator powers on anyway and burns **~400 µA** until software shuts it down by writing 1 to `VREG.HIZ`. **There is no external "LDO-only" mode.** Low-power/linear mode is a software mode capped at 1 mA and cannot be used with an external DVDD. Fig 21 is the only external-supply option. This is the escape hatch if the Abracon inductor is unobtainable — at the cost of an external 1.1 V rail. ### Board-level input supply Not on-chip, but what RPi's minimal board does: micro-USB VBUS 5 V → **NCP1117ST33T3G** fixed 3.3 V LDO (1 A), 10 µF in (C1) / 10 µF out (C5). ## 4. Crystal **12 MHz**, and RPi specifies **Abracon ABM8-272-T3** — same crystal as Pico and Pico 2. | Parameter | Value | |---|---| | Frequency | 12.000 MHz, fundamental AT | | Tolerance | ±30 ppm @25 °C | | Stability | ±30 ppm | | **ESR (R1)** | **max 50 Ω** | | Shunt capacitance C0 | 3.0 pF | | **Load capacitance CL** | **10 pF** | | Drive level | 10–200 µW | | Aging | ±5 ppm first year | | Operating temp | −40…+85 °C | Load network: **C3 = C4 = 15 pF** → 7.5 pF series, plus ~3 pF assumed pin/track parasitic → 10.5 pF, "close enough to the target of 10 pF." Keep XIN/XOUT short. XIN = QFN-60 pin 21, XOUT = pin 22, both in the IOVDD domain. **Series damping resistor R2 = 1 kΩ**, chosen together with the 50 Ω max ESR "to prevent the crystal being over-driven and being damaged when using an IOVDD level of 3.3 V." > However, if IOVDD is less than 3.3 V, then the drive current of the XIN/XOUT pins is reduced, and you will find that the amplitude of the crystal is lower, or may not even oscillate at all. In this case, a smaller value of the series resistor will need to be used. XOSC is powered from IOVDD, and the whole ABM8 + 1 kΩ combination is tuned for 3.3 V. Any other IO voltage needs re-tuning and temperature testing. If you can't source the part, RPi says contact `[email protected]`. **A crystal is not mandatory.** §8.2.1: you can drive an external clock straight into XIN (CMOS square wave at IOVDD) and disable the oscillator — **up to 50 MHz**. Crystal range is 1–50 MHz (RP2040 topped out at 15). The PLL needs ≥5 MHz, `clk_ref` max 25 MHz (divide above that). You can't tap XOSC out of XIN/XOUT — use `clk_gpclk0–3`. **But something must clock it to boot**: §5.2.8.1 — "BOOTSEL mode requires either a crystal attached across the XIN and XOUT pins, or a clock signal from an external oscillator driven into the XIN pin." The bootrom assumes 12 MHz and derives a precise 48 MHz for USB. ## 5. Boot and programming The bootrom samples **QSPI CSn** shortly after reset. CSn is initialised output-disabled with an internal pull-up: - **CSn high** → normal boot from flash. - **CSn pulled low externally** → BOOTSEL mode. "You must drive the chip select low with a sufficiently low impedance to overcome the internal pull-up. **A 4.7 kΩ resistance to ground is a good intermediate value.**" - **QSPI SD1** then picks the bootloader: left pulled low → **USB** (UF2 mass storage + PICOBOOT). Driven high → **UART boot**, TX on QSPI SD2, RX on QSPI SD3, fixed **1 Mbaud**. RP2354-specific behaviour, §14.3: - Driving CSn low to select BOOTSEL "**harmlessly selects the internal flash die but does not issue commands to it**." - "**Even with the chip select asserted low, the internal flash die maintains a high-impedance state on its SD0 through SD3 pins if there are no transitions on SCK**" — so you can hold CSn asserted throughout UART boot. - "**Internal flash can be programmed via UF2 drag-and-drop download using the USB BOOTSEL mode.**" - It can also be programmed externally by **holding RP2350 in reset via RUN (active low) and driving the QSPI signals from an external programmer**. ### The BOOTSEL circuit - **R6 = 1 kΩ** in series from QSPI_SS to pushbutton SW1 ("USB_BOOT") to GND. "It is important to include resistor R6, as this allows the QSPI_SS pin to safely over-drive the applied pull-down when the RP2350 starts booting." - **R1 (10 kΩ pull-up on QSPI_SS) is marked DNF.** "We have found that with this particular flash device, the external pull-up is unnecessary. However, if a different flash is used, it may become important to be able to insert a 10 kΩ resistor here, so it has been included just in case." → **RP2354A needs no board-level CS pull-up.** - Place R1/R6 (and R9/R10) close to the flash to keep track lengths short. - Reset sequence: hold QSPI_SS low, then toggle **RUN** (pin 26, Digital In FT, pull-up at reset, active-low). The minimal board has a second button SW2 on RUN. - Buttons aren't strictly required — "the signals are still available on the headers… though the BOOTSEL button would have to be replaced with a header or similar if USB boot mode was required." ### SWD - **SWCLK = QFN-60 pin 24** (Digital In FT, IOVDD domain, pull-up at reset) - **SWDIO = pin 25** (Digital IO FT, pull-up at reset) - Multi-drop SW-DP, ADI v6. §3.5.1: "**The SW-DP defaults to the Dormant state at power-up or assertion of the external reset (RUN) pin. A Dormant-to-SWD sequence must be issued before beginning SWD operations.**" Connect sequence opens with at least 8 SWCLK cycles with SWDIO high. - SW-DP and RP-AP are in the always-on domain and available right after POR. **All other APs only come up once POWMAN has powered the switched core, the OTP PSM has read critical flags, and `clk_sys` is running.** This is a real gotcha versus STM32 SWD. - No series resistors or external pull-ups specified. RPi's minimal board brings SWD out on the 2.54 mm header J3 plus an optional 3-pin horizontal JST **SM03B-SRSS-TB(LF)(SN)** (J4). ## 6. 5 V tolerance — narrower than the headline Datasheet Table 1426 defines the "(FT)" pin type: > These pins are described as Fault Tolerant, which in this case means that very little current flows into the pin whilst it is below 3.63 V and IOVDD is 0 V. Additionally, **they will tolerate voltages up to 5.5 V, provided IOVDD is powered to 3.3 V.** These pins have enhanced ESD protection. HBM 4 kV on FT pins vs 2 kV elsewhere. Absolute maximum (Table 1433): | IOVDD | VPIN_FT max | |---|---| | **3.3 V** | **5.5 V** | | 2.5 V | 4.2 V | | 1.8 V | 3.63 V | | **0 V** | **3.63 V** | On the QFN-60 (RP2350A / RP2354A): - **5 V tolerant (FT):** **GPIO0 … GPIO25**, plus **RUN** (26), **SWCLK** (24), **SWDIO** (25). - **NOT tolerant:** **GPIO26_ADC0 … GPIO29_ADC3** (pins 40–43) — these are standard pads, abs max IOVDD + 0.5 V. ADC analogue inputs must never exceed IOVDD or current flows through the ESD diodes. - **NOT tolerant:** **QSPI_SS / QSPI_SCLK / QSPI_SD0–SD3** (55–60), in the QSPI_IOVDD domain. USB_DP/USB_DM are in the USB_OTP_VDD domain, also not FT. **The caveat that matters:** tolerance only exists while IOVDD is powered at 3.3 V. Hot-plugging a live 5 V signal into an unpowered board exceeds abs max (3.63 V with IOVDD at 0 V) and can damage the pad. Running IOVDD at 1.8 V kills 5 V tolerance entirely. For a printer board this means: endstops and filament switches on GPIO0–25 are genuinely 5 V-safe in normal operation, but **thermistors and anything else on the ADC pins are not**, and you still want protection on anything that can be live while the board is off. ## 7. RP2040 → RP2354A migration checklist 1. **Not pin compatible.** QFN-60, 7×7 mm BSC, 0.400 mm pitch BSC, 0.80/0.85/0.90 mm thick, exposed pad 3.35/3.40/3.45 mm, MSL1, JEDEC J-STD-020E & 033D. RP2040 is QFN-56 with a different pinout. 2. **The regulator is the big change.** RP2040's 2-pin 100 mA LDO becomes a 5-pin 200 mA SMPS (VREG_VIN, VREG_LX, VREG_FB, VREG_PGND, VREG_AVDD) needing the polarity-marked Abracon inductor, tight-spec 4.7 µF CIN/COUT, a 33 Ω/4.7 µF RC on VREG_AVDD, and a prescriptive layout placed first. 3. **New/split rails to route:** QSPI_IOVDD separate from IOVDD; USB_OTP_VDD always powered even with USB unused; VREG_AVDD a separate low-noise 3.3 V. 4. **Delete the external flash**, its decoupling and its CS pull-up — **but keep the BOOTSEL switch on QSPI_SS**. 5. **QSPI_IOVDD locked to 3.3 V**, and IOVDD too if you use CS1. No 1.8 V IO option. 6. **Second chip select is new** (QMI CS1n on GPIO0/8/19), 16 MB per CS, usable for extra flash or QSPI PSRAM — needs an external pull-up because GPIOs reset pulled down. 7. **5 V tolerance is new** on GPIO0–25 / RUN / SWCLK / SWDIO, conditional on IOVDD = 3.3 V. 8. **Crystal:** still 12 MHz nominal, but XOSC now takes 1–50 MHz, or a CMOS clock into XIN up to 50 MHz. 9. **USB unchanged:** 27 Ω series resistors close to the chip (R7/R8), ~90 Ω differential. RPi's minimal board uses 0.8 mm traces with 0.15 mm gap on 1 mm FR4. 10. **Boot/security model is much larger** — secure boot, 8 KB antifuse OTP, partition tables, A/B images, UART boot, OTP boot. Read Appendix E errata and check your stepping. ## 8. Stepping identification `CHIP_ID.REVISION`, or `rp2350_chip_version()`: | Value | Stepping | |---|---| | `0x2` | A2 — original, has E9 | | `0x3` | A3 — hardware fixes (E9, E3), never sold as bare silicon | | `0x8` | **A4 — current shipping part** | A4 has **no hardware changes vs A3**; A4 adds boot ROM fixes (E18 fix, E24 mitigation, E25 fix, and the E14 CS1 fix). The stepping is also printed on the package. A2 production has ceased and A2 inventory was withdrawn from channel, so new stock in 2026 is A4. See [[Klipper Compatible MCU Comparison]] for the full E9 story. # TODO - ==Confirm JLCPCB stocks the Abracon AOTA-B201610S3R3-101-T and ABM8-272-T3, or plan to hand-supply both== - ==Check current JLCPCB availability / lead time for RP2354A specifically — as of Aug 2025 forum reports it was RP2350A only with ~35 day lead on 2350B/2354B== - ==RP2354A thermal figures still TBD in the datasheet — re-check Table 1423 on the next datasheet build== - ==Datasheet currency: the canonical URL currently serves build 2025-07-29 even though the hardware design guide was rebuilt 2026-08-24. Re-check for a newer datasheet build before committing a layout.== - ==Decide whether 2 MB internal flash is enough, or whether the design wants CS1 PSRAM — if so, budget the 10 kΩ pull-up and pick CS1 on GPIO0 to stay on the well-trodden path== - ==Verify the QSPI_IOVDD range discrepancy (§14.3 says 2.7–3.6 V, Table 1441 says 2.97–3.63 V) doesn't matter for a 3.3 V design — it shouldn't== # References - [[Klipper Compatible MCU Comparison]] — why RP2350/RP2354 over RP2040 and STM32F042 - [[STM32G0B1CBT6 LQFP-48 Layout Playbook]] — the STM32 equivalent of this note - [[JLCPCB Design Notes]] - [[KiCad 9 MCU Board Design Workflow]] - [[PCB Layout Rules to Never Break]] ## Source caveats Extraction was done 2026-09-18 against the *Hardware design with RP2350* text and the live RP2350 datasheet PDF. Register-level chapters (PIO, DMA, peripherals) were not reviewed. Sections read in full: §1.2.3, §3.5.1, §5.2.8, §6.1, §6.2.3.5, §6.3, §8.2, §14.1–14.5, §14.8, §14.9, Appendices C and H. ==The A4 PCN and PCN 32 PDFs were located but not read — fetch them if the stepping story needs to be airtight for a production run.==